Oki Electric Industry Co., Ltd.

Oki Electric Co., Ltd.

Shooji Kitazawa

Teruhiro Harada

Hiroshi Kuwabara

Takashi Ono

Yasuhiro Fukuda

Satoru Namaki

Hitoshi Kokubun

Keiichiro Takeda

Yuichi Ashizawa

A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M,M,. . . whose gates are connected to word lines WL,, WL,. . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL,SVL,SVL,SBL,. . . which connect the connection nodes between the sources and drains of the memory cell transistors M,M,. . . in the column direction, a power source line PV,which supplies a prescribed electric potential to these column lines, first and second sense amplifiers which detect the electric potential level of the column lines or a current that flows through the column lines, sense column line selection means SS,SS,SS,SS,and,which connect column lines SBL,and SBL,connected to one terminal of selected memory cell M,and one terminal of selected memory cell M,respectively, to the first and second sense amplifiers A,and A,respectively. In this case, the memory cell M,is separated from the memory cell M,by a prescribed number of memory cells on the same memory cell row. This nonvolatile semiconductor storage apparatus further has power source supply column line selection means DS,DS,DS,DS,. . . which connect the column lines connected to the other terminals of the two selected memory cells to the power source line.

Non-volatile semiconductor memory capable of reducing parasitic current

A non-volatile semiconductor memory apparatus having a memory matrix of inter-column arrangement type configuration divided into several segments performs a read operation based on a system that causes a current to flow into sense amplifiers from data lines. In this non-volatile semiconductor memory, memory cell transistors configured as memory cells are serially connected to form multiple memory rows. Word lines connect the gates of the transistors constituting the memory cells of each memory row. First column lines and second column lines connect the connection nodes between the memory cell transistors. The word lines and the first and second column lines constitute a memory array. Bit lines are connected to the second column lines, respectively. A bias electric potential supply line is connected to the first column lines via select transistors, respectively. A multiplexer circuit includes select transistors which select two bit lines as a pair from the bit lines, and connect the selected two bit lines to a data bus pair. Sense amplifiers are connected to the data buses, respectively.

Non-volatile semiconductor memory and method for reading data stored

A read-only semiconductor memory device including memory elements arranged in a principal surface of the semiconductor substrate in a matrix to form MOS transistors. Each of the memory elements has first and second electrode regions formed in the principal surface so as to respectively constitute the first and second electrodes, insulative layers formed on the principal surface, and a control electrode layer formed via the insulative layers on the principal surface to constitute the control electrode. The control electrode layer is commonly connected to memory elements in the lateral direction of the matrix. The first and second electrode regions are respectively arranged such that any adjacent two in the vertical direction of the memory elements electrically share the first and second electrodes, respectively. Each of the first electrode regions is interconnected to the first electrode region of one of the elements adjacent thereto in the lateral direction. The second electrode regions are also interconnected similarly. The device further includes first and second conductor members each formed on the insulative layers so as to electrically interconnect the first and second electrode regions, respectively, of the elements in the vertical direction. The boundaries between the control electrode layer and the first and second electrodes are defined in the lateral direction substantantially in parallel thereto.

Nonvolatile semiconductor memory device of shared contact scheme not

A method of operating an EPROM which has a word line, a predecode circuit having an ou tput terminal and a transistor having a first electrode connected to the output terminal of the predecode circuit, a second electrode connected to a word line and a control gate. The method of operating the EPROM includes generating a selection signal and an inverted signal thereof in accordance with an internal address signal, and generating a delayed signal responsive to the selection signal and the inverted signal so that the delayed signal rises by a predetermined time delay behind a rising of the selection signal and rapidly falls substantially simultaneously with a rising of the inverted signal. Thereafter the potential of the selection signal is boosted in accordance with a potential of the delayed signal and the boosted selection signal is supplied to the control gate of the transistor connected between the predecode circuit and the word line.

Method of operating an EPROM including delaying and boosting steps

An electrically erasable nonvolatile semiconductor device of a high density of integration includes a memory matrix array formed of a plurality of MOS memory transistors. In an erasing operation, a voltage to turn off one selected MOS memory transistor is applied to the control gate electrode of the selected MOS memory transistor. At the same time, a voltage near the breakdown voltage of the selected MOS memory transistor is applied to the first electrode (e.g.--source electrode) of the selected MOS memory transistor and a predetermined voltage is applied to the second electrode (e.g.--drain electrode) of the same MOS memory transistor.

EEPROM device including read, write, and erase voltage switching circuits

In a memory MOS semiconductor memory device comprising a memory matrix having semiconductor memory elements arranged in rows and columns, the memory elements in the same rows being connected to the respective word lines, and the memory elements in the same columns being connected to the respective source lines and data lines. A row decoder outputs a row selection signal to one of the rows of the memory elements through the word lines, while a column decoder outputs a column selection signal to one of the columns through the source lines. A common data line is electrically coupled to a plurality of the data lines, a constant voltage is applied from a common circuit to the data lines through the common data line, and the current required for maintaining the common data line at a constant voltage is detected by a detecting circuit.

MOS semiconductor memory device

In a semiconductor device having an external input terminal, a first insulated-gate field-effect transistor formed on a semiconductor substrate, and having a gate connected to the input terminal, and a second insulated-gate field effect transistor having a drain connected to the gate of the first insulated-gate field-effect transistor, and having a gate and source connected to a reference voltage source, the ratio W/L of the channel width W to the channel length L of the second insulated-gate field effect transistor is not less than 12.

Encapsulated FET semiconductor device with large W/L ratio

Am EPROM system comprising a memory cell array formed of a matrix of non-volatile semiconductor memory cells, each having a control gate and a floating gate, and storing electric charges on the floating gate, and a word line drive circuit driving respective word lines connected to the control gates of the respective memory cells. The word line drive circuit comprises a delay circuit for delaying a first selection signal, a boosting capacitor having a first electrode connected to the first selection signal and a second electrode connected the output of the delay circuit, and MOS transistors each having a gate electrode connected the second electrode of the boosting capacitor, a first electrode connected to receive a second selection signal and a second electrode connected to a word line.

Erasable and programmable read-only memory system

A read-only semiconductor memory device including memory elements arranged in a principal surface of the semiconductor substrate in a matrix to form MOS transistors. Each of the memory elements has first and second electrode regions formed in the principal surface so as to respectively constitute the first and second electrodes, insulative layers formed on the principal surface, and a control electrode layer formed via the insulative layers on the principal surface to constitute the control electrode. The control electrode layer is commonly connected to memory elements in the lateral direction of the matrix. The first and second electrode regions are respectively arranged such that any adjacent two in the vertical direction of the memory elements electrically share the first and second electrodes, respectively. Each of the first electrode regions is interconnected to the first electrode region of one of the elements adjacent thereto in the lateral direction. The second electrode regions are also interconnected similarly. The device further includes first and second conductor members each formed on the insulative layers so as to electrically interconnect the first and second electrode regions, respectively, of the elements in the vertical direction. The boundaries between the control electrode layer and the first and second electrodes are defined in the lateral direction substantially in parallel thereto.

Semiconductor fet with long channel length

In a current sense circuit for detecting a read current from a selected memory cell in a memory cell matrix of a ROM, each of a first series circuit and a second series circuit comprises: a current supply means having a first main electrode connected to a power supply; a first MOS FET having a first main electrode connected to the second main electrode of the current supply means; and a second MOS FET having a first main electrode connected to the second main electrode of the first MOS FET, a second main electrode connected to a second power supply, and a gate electrode connected to the first main electrode of the first MOS FET. The gate electrode of the first and the second MOS FETs of the reference voltage generator are connected together; the gate electrodes of the first MOS FETs of the first and second series circuits are connected together; and the ratio of the current driving capability between the first MOS FET of the first series circuit and the first MOS FET of the second series circuit is substantially equal to the ratio of the current driving capability between the second MOS FET of the first series circuit and the second MOS FET of the second series circuit.

Current sense circuit for a ROM system

The invention concerns a method for electrically erasing data stored in a FAMOS-type EPROM. That is, in an Electrically Programmable Read Only Memory of the Metal Oxide Semiconductor type in which a Floating gate is employed as a memory element and in which data-writing is effected by charge injection from a channel Avalanche current, the invention concerns a method for effectively removing such channel-injected charge from a subject written floating gate. The method specifically entails the injection into the written gate of neutralizational opposing-polarity hot carriers from a generated reverse avalanche current between th MOS drain and substrate. The drain avalanche, however, is limited to 'non-breakdown' levels by a technique which, in addition to appropriate drain biasing, includes suitable source and control-gate biasing so as to essentially prevent the flow of channel current during erasure. The method is applicable to either n-channel or p-channel devices and does not require the use of a separate select transistor.

Method for erasing data in a semiconductor memory device

A MOS ROM system is arranged such that during a readout operation a current flows from at least one data line selected from among a plurality of data lines. The read and sense circuit detects a memory state of a selected memory cell based on the amount of inflow current. A non-selected memory cell does not contribute to a word line load capacitance, and the word line load capacitance upon switching word lines can be reduced. A signal transfer rate can therefore be increased, and a data read rate can thereby be speeded up. Moreover, a read and sense circuit for a ROM is adapted such that first and third MOS transistors and a first current supply circuit, and second and fourth MOS transistors and a second current supply circuit are associated with each other, and each connected in series betweeen a low supply voltage and high supply voltage. The input side of the ROM can be kept at a stabilized low potential, and information stored in a selected memory element can be read out based on the value of an inflow current into the read and sense circuit.

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Tokyo, Japan

Shooji Kitazawa