International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Merlyn Mind, Inc.

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Avago Technologies International Sales Pte. Limited

Globalfoundries U.S. 2 LLC

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Freescale Semiconductor,inc.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Xio Research, Inc.

Globalfoundries U.S. Inc.

Shom Ponoth

David V Horak

Chih-Chao Yang

Kangguo Cheng

Theodorus E Standaert

Charles W Koburger, Iii

Tenko Yamashita

Balasubramanian S Haran

Ali Khakifirooz

Takeshi Nogami

Ruilong Xie

Bruce Bennett Doris

Steven J Holmes

Balasubramanian Pranatharthiharan

Marc Adam Bergendahl

Terry Allen Spooner

Qing Liu

Elbert Emin Huang

Satyanarayana Venkata Nitta

Daniel C Edelstein

Akira Ito

Nicolas J Loubet

Raghavasimhan Sreenivasan

Shyng-Tsong Chen

Prasanna Khare

Xiuyu Cai

David Lee Rath

Stefan Schmitz

Su Chen Fan

Maud Vinet

Satya Venkata Nitta

Son Van Nguyen

Arvind Kumar

Sanjay C Mehta

Thomas N Adam

Hosadurga K Shobha

Griselda Bonilla

Lawrence Alfred Clevenger

Juntao Li

Veeraraghavan S Basker

Christian Lavoie

Praneet Adusumilli

Kevin Shawn Petrarca

Wai-Kin Li

JunJun Li

John Anthony Fitzsimmons

Pranita Kulkarni

Pranita Kerber

Emre Alptekin

Muthumanickam Sankarapandian

Douglas C La Tulipe, Jr

Sharad C Sundararajan

Aditya Vempaty

Simon Gaudet

Alexander Reznicek

Reinaldo Ariel Vega

Christopher J Penny

Baozhen Li

Kern Rim

Herbert Lei Ho

Ravikumar Ramachandran

John Edward Barth, Jr

Kisik Choi

Babar Ali Khan

Huiming Bu

Christos Dimitrios Dimitrakopoulos

Yunpeng Yin

Vincent James McGahay

Ravindranath Kokku

Kaushik Chanda

Kaushik Arun Kumar

Shahab Siddiqui

Samuel S Choi

Michael Wayne Lane

Jin Wook Lee

Kehan Tian

Cathryn Jeanne Christiansen

Deepak Anantarao Kulkarni

Effendi Leobandung

Ghavam G Shahidi

Chanro Park

Ramachandra Divakaruni

Keith Kwong Hon Wong

Sivananda K Kanakasabapathy

Soon-Cheon Seo

Dae-Gyu Park

Johnathan E Faltermeier

Stephen Edward Greco

Gregory Breyta

Leathen Shi

Vidhya Ramachandran

Nicholas C M Fuller

Zhibin Ren

Stephan Grunow

Maxime Darnon

Wei-Tsu Tseng

Charan Veera Venkata Satya Surisetty

Michael Beck

Daniel T Pham

Anthony David Lisi

A method performed by a remote-control unit (RCU) of managing a content transfer to or from integrated output devices (IODs) in a physical room is disclosed. The content transfer involves moving application context of a computer application with which a user can interact, which includes a computer object being operated on and relevant metadata. The RCU is programmed to recognize simple user instructions for the content transfer and perform the content transfer from a source device to a target device in real time, regardless of data transfer protocols specific to computer applications. Specifically, the RCU is programmed to obtain source data from the source device, generate updated source data by combining the source data with one or more commands specifying how the source data is to be handled based on a session mode indicating a type of activity being performed in the physical room, and transmit the updated source data to the target device for further user interaction.

Content transfer among remote-control units and integrated output devices

A component management server computer ('server') and processing methods are disclosed. In some embodiments, the server is programmed to continuously receive input data regarding what is happening in the physical room from one or more input devices. The server is programmed to then detect an utterance of a spoken word from the input data and generate one or more sound metrics based on the input data. Based on the sound metrics as applied to certain criteria, the server is programmed to activate a component, such as an input device, variable, software system, or output device, and cause one or more output devices to execute an action that alerts a user of the activated component. The server can also be programmed to turn on, off, up, or down any of the components based on the activated component.

Automatic adaptation of multi-modal system components

A method of customizing contextual controls of a remote-control unit (RCU) having a plurality of user interface elements is disclosed. A processor within the RCU receives context information from an integrated output device that includes an output mechanism, the context information being related to an active application being run on the integrated output device and an active object being presented by the active application. The processor determines a set of actions that can be performed on the active object within the active application. The processor dynamically maps actions to user interface elements of the RCU based on the context information. The processor receives a selection of a user interface element and sends a request from the RCU to the integrated output device specifying an action mapped to the user interface element to be performed on the active object and the active application.

Context-sensitive customization of remote-control unit

Media hub

A device management server computer ('server') and processing methods are disclosed. In some embodiments, the server is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.

Managing connections of input and output devices in a physical room

A device management server computer ('server') is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.

A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Fin-shaped field effect transistor and capacitor structures

Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.

Laterally diffused MOSFET on fully depleted SOI having low on-resistance

A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.

Three dimensional LVDMOS transistor structures

A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.

Three dimensional monolithic LDMOS transistor

A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

Interconnect structures incorporating air gap spacers

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Size-filtered multimetal structures

A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

Self-aligned source/drain contacts

Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

FDSOI LDMOS semiconductor device

A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.

Replacement gate structures for transistor devices

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Clifton Park, NY, United States of America

Shom Ponoth