Xilinx, Inc.

Sholeh Diba

Wei-Yi Ku

Napoleon W Lee

Derek R Curd

Kameswara K Rao

Neil G Jacobson

Hy V Nguyen

Jeffrey H Seltzer

Mihai G Statovici

Jesse H Jenkins, Iv

Qi Lin

Ronald J Mack

Anders T Dejenfelt

George H Simmons

Robert A Olah

Joshua M Silver

Prasad L Sastry

Diane M Hoffstetter

A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.

Clock enable control circuit for flip flops

An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Overridable data protection mechanism for PLDs

A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.

Two transistor flash EEprom cell and method of operating same

Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

Fast signal path for programmable logic device

A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

Reset circuit for a programmable logic device

A macrocell for a programmable logic device includes private product term assignments to provide various functions including set and reset, output enable, clocking, and inversion. Each of these additional functions is provided by assigning one of the product terms associated with the macrocell to perform one of these functions locally. By means of additional logic circuitry these functions are achieved either singly or in combination for a particular macrocell, thus improving macrocell flexibility and in some cases conserving pins of the chip of which the programmable logic array is a part.

High speed product term assignment for output enable, clock, inversion

An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Programmable logic device with configurable power supply

In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

Method and apparatus for reducing coupling switching noise in

A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.

Macrocell architecture with high speed product terms

A macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device. The macrocell allows a variable number of product terms to be retained by the macrocell, and a variable number of product terms to be exported to a second macrocell. The direction in which the product terms are exported can be controlled. The macrocell further allows a variable number of product terms to be received from a third macrocell and routed either to the output terminal of the first macrocell or to the second macrocell in combination with those product terms exported from the first macrocell. Methods for routing product terms using macrocells within a programmable logic device are also provided.

High speed product term allocation structure supporting logic iteration

A multiplexer for a programmable logic device (PLD) includes a control line decode circuit that substantially reduces the number of control lines necessary to program a multiplexer. Each multiplexer input line is programmably connected to at least three output lines to increase the number of routing options. A TTL buffer circuit located at the output of the multiplexer provides the user with various output signal options, whereas a word line driver coupled to the TTL buffer circuit increases signal drive. Local feedback signals are provided to the multiplexer to increase PLD functionality. Signals from the I/O pads are routed directly to the multiplexer rather than the UIM, thereby improving PLD speed. Moreover, using the multiplexer minimizes the number of input lines because the UIM is still available for routing connections. Therefore, the present invention provides both fast cycle time and fast multiple level logic.

Multiplexer for programmable logic device

The present invention provides a configurable sense amplifier for a programmable logic device (PLD) that can be turned on or off as needed. Specifically, a latch stores an enable or disable state which respectively connects or disconnects the sense amplifier to a voltage source Vcc. In this manner, the sense amplifier remains on or off until the latch is reset. In one embodiment of the present invention, a reset circuit provides a predetermined value to the latch and a pass transistor to prevent floating during a power-on operation.

Power-managed sense amplifier for programmable logic device

A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

Wordline driver for flash PLD

An integrated circuit one shot circuit provides relatively long duration (hundreds of nanoseconds up to a millisecond) output pulses without the need for excessively large transistors. The one shot circuit includes a pull up and a pull down device connected to the one shot circuit's input terminal, with a latch connected to a node between the pull up and pull down devices. The output terminal of the latch is connected to the input of a Schmitt trigger. One terminal of a grounded capacitor is connected between the latch output terminal and the Schmitt trigger input. The output terminal of the Schmitt trigger is connected through an inverter to one input terminal of a NAND gate, the other input terminal of which is connected to the one shot circuit's input terminal. A feedback line connects the output terminal of the NAND gate to the gate of a depletion mode transistor which is between the pull up and pull down devices. This provides a glitch free long duration output pulse using conventional CMOS transistor fabrication technology in a large scale integrated circuit.

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Los Gatos, CA, United States of America

Sholeh Diba