Kabushiki Kaisha Toshiba

Shojiro Mori

Nobu Matsumoto

Hiroshi Hatada

In graphic data representing a symbolic layout for a semiconductor integrated circuit, a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles are set. First, the graphic data is cut along said first cutting lines to produce a plurality of first segment data items. These first segment data items are each compacted in the direction of the second cutting line. These compacted first segment data items are connected according to the first cutting lines. This connected first segment data is cut along the second cutting lines to produce a plurality of second segment data items. These second segment data items are each compacted in the direction of the first cutting line. These compacted second segment data items are connected to one another to produce a compacted mask layout.

Method of and apparatus for generating mask layouts

A semiconductor device formed by using a standard cell system is a semiconductor device using a multi-layered wiring system. At this time, inter-cell wirings for electrically connecting different standard cells are formed of only a conductive layer which is disposed above a conductive layer constituting intra-cell wirings of the standard cells. Connection between the inter-cell wirings is made above an occupied area of the standard cells on the semiconductor substrate so as to eliminate a channel region.

Semiconductor device using standard cell system

A semiconductor integrated circuit device includes a plurality of standard cell rows each including first standard cells and wiring regions each of which is arranged between any two adjacent ones of the standard cell rows and in which cell connection wirings are formed, wherein the standard cell row includes at least one second standard cell and the second standard cell includes an internal wiring region in which cell connection wirings are formed.

Semiconductor integrated circuit device having standard cells including

A transfer circuit for the operation test of an LSI system inlcudes a mode setting section for selectively setting a first or second operation mode, a plurality of first shift register circuits connected to the input terminals of function blocks of the LSI system to respectively latch input data to the function blocks in a parallel fashion in the first operation mode and shift the input data in the second operation mode, a plurality of second shift register circuits connected to the output terminals of the function blocks of the LSI system to respectively latch output data of the function blocks in a parallel fashion in the first operation mode and shift the output data in the second operation mode, and a serial transfer line for serially connecting the first and second shift register circuits.

Transfer circuit for operation test of LSI systems

A logic circuit according to this invention has a logic section. First input terminals of first to third EX OR gates are respectively connected to output terminals of preselected logic elements among the logic elements which constitute the logic section. Output terminals of the first and second EX OR gates are connected to second input terminals of the second and third EX OR gates. The functional test for this logic circuit is performed by inputting test pattern signals to the logic section and by comparing output signals of the logic section and an output signal of the third EX OR gate with the expected values.

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Yokohama, Japan

Shojiro Mori