Hitachi, Ltd.

Shinkawa Ltd.

Texas Instruments Corporation

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Longitude Semiconductor S.a.r.l.

Vlsi Engineering Corporation

Shoji Wada

Hitoshi Miwa

Yutaka Kobayashi

Kazumasa Yanagisawa

Goro Kitsukawa

Atsushi Nozoe

Masayuki Nakamura

Tetsurou Matsumoto

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Kohei Seyama

David R Brown

Ken Saitoh

Hiroshi Kikuchi

Kazuyuki Miyazawa

Shoji Kubono

Masaya Muranaka

Yukihide Suzuki

Makoto Morino

Yuji Yokoyama

Kazuya Ito

Sinichi Miyatake

Masahiro Ogata

Kanehide Kenmizaki

Yoshihisa Koyama

Hidetomo Aoyagi

Tetsuya Kitame

Masahiro Katayama

Yasuhito Ichimura

Nobuhiko Ohno

Yuji Eguchi

Seiichi Shundo

The present invention is provided with: a stage having a placing surface for a semiconductor chip, and a first heater heating the placing surface; a bonding head having a contact surface to be in contact with an subject, a second temperature sensor measuring the temperature of the subject via the contact surface, and a second heater heating the contact surface, said bonding head being driven in at least the orthogonal direction with respect to the placing surface; and a control unit measuring the temperature of the subject based on a temperature detection value of the second temperature sensor, said temperature detection value having being obtained by heating the placing surface and the contact surface to predetermined target temperatures, respectively, by means of the first and second heaters, then bringing the contact surface into contact with the subject in a state wherein heating by the second heater is stopped.

Mounting apparatus and temperature measurement method

An apparatus for manufacturing a semiconductor device includes a base portion, a bonding stage arranged on the base portion and having a placement surface for placing a substrate; and one or more connecting members which connect the base portion and the bonding stage, wherein at least one of the one or more connecting members is a connecting plate that deflects following the expansion and contraction of the bonding stage in the plane direction caused by a temperature change.

Apparatus for manufacturing semiconductor device

The present invention has: a heater; and a bonding tool having a lower surface on which a memory chip is adsorbed; and an upper surface attached to the heater, and is provided with a bonding tool which presses the peripheral edge of the memory chip to a solder ball in a first peripheral area of the lower surface and which presses the center of the memory chip () to a DAF having a heat resistance temperature lower than that of the solder ball in a first center area. The amount of heat transmitted from the first center area to the center of the memory chip is smaller than that transmitted from the first peripheral area (A) to the peripheral edge of the memory chip. Thus, the bonding apparatus in which the center of a bonding member can be heated to a temperature lower than that at the peripheral edge can be provided.

Bonding apparatus including a heater and a cooling flow path used for stacking a plurality of semiconductor chips

A flux reservoir apparatus () includes a stage () having a recessed portion () for reserving flux () therein and a flux pot () composed of an annular member having a through hole () through which the flux () flows, the flux pot arranged to move back and forth on the surface () of the stage () to feed the flux () into the recessed portion () and to smooth the surface of the flux (), in which the through hole () is an elongated hexagonal hole with a length greater than the width of the recessed portion () in the direction perpendicular to the back-and-forth direction, and in which the bottom surface of a flux pot main body () is a chevron surface. This reduces leakage of the flux () in the flux reservoir apparatus ().

Flux reservoir apparatus

Provided is a bonding stage including: a rigid block () having a plurality of projections () on a surface () of the base body, upper surfaces of the projections being flat; a flat plate () fixed to supporting surfaces () on the projections (); a ceramic plate () suctioned and fixed to the flat plate (); a plate-shaped heater () disposed on a side of the rigid block () of the flat plate (); and coil springs () disposed between the heater () and the rigid block (), the coil springs () bringing the heater () into close contact with a surface of the flat plate () on the side of the rigid block ().

Bonding stage and method of manufacturing the same

Disclosed herein is a device that includes a first wiring provided as a first-level wiring layer and elongated in a first direction; and a first wiring pad provided as the first-level wiring layer, the first wiring pad being rectangular and including a first side edge that is elongated in the first direction and a second side edge that is elongated in a second direction crossing to the first direction, the first side edge being greater in length than the second side edge, the first wiring pad being greater in length in the second direction than the first wiring.

Semiconductor device having wiring pad and wiring formed on the same wiring layer

A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV). The timing of the SAOV signal is based upon the location of the memory array (402a-402h) which is being accessed in the sense operation.

Address controlled sense amplifier overdrive timing for semiconductor

A semiconductor memory is provided with a main amplifier circuit that is capable of selectively driving and precharging two I/O buses in conjunction with a write amplifier. The main amplifier circuit includes a separation and precharge section and an activation section. The activation section drives a signal for activating the first section to precharge the two I/O signals only when the two I/O buses are not being separated. The main amplifier circuit also includes both a main output bus and a test output bus. In so doing, the semiconductor memory can operate in a normal mode and a test mode. In the test mode, twice as many memory cells of the semiconductor memory can be accessed simultaneously, thereby reducing test time. The semiconductor memory, which can be one of many different data widths, has different sized output buses associated with each data width. Output buses with a relatively large capacitance can be produced with a large width, giving them a relatively small resistance. Conversely, output buses with a relatively small capacitance can be produced with a small width, giving them a relatively large resistance. As a result, a time constant for the output buses associated with each of the different widths is very similar.

Main amplifier circuit and input-output bus for a dynamic random access

A circuit for testing a memory cell array 100. The circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a failure signal output line 108. A shift register 110, which includes a plurality of latches, a clock signal input 114, and an output line 116, is connected to the failure signal output line of the test circuit. The circuit also includes a three-state output buffer driver 118, the buffer driver including a data input line, a failure signal input line, and a data output line. The failure signal line of the buffer driver is connected to the output line of the shift register 110. Upon detecting a defective memory cell in the array, the test circuit produces a failure signal on the failure signal output line 116 of the test circuit. The failure signal is then sent to the shift register 110 causing the buffer driver 118 to enter a high-impedance state in response to said failure signal. The shift register 110 comprises a number of latches in accordance with the desired latency variability of the system or test equipment using the test circuit.

Memory array test circuit and method

A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.

Memory configuration circuit and method

A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

Semiconductor memory system

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Dynamic Random Access Type Semiconductor Device

A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.

Non-inverting buffer circuit device and semiconductor memory circuit

Testing method for a semiconductor memory device

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Bi-CMOS semiconductor memory device, including improved layout structure

Growing community of inventors

Tokyo, Japan

Shoji Wada