Fujitsu Corporation

Shoji Temma

Jun Funaki

The state monitoring system includes a plurality of objects of monitor of the same kind, a monitor unit for monitoring the plurality of objects of monitor to determine if any of them malfunctions, and a consolidating unit interposed between the plurality of objects of monitor and the monitor unit. The consolidating unit consolidates alarm signals sent from the objects of monitor for each group of objects of monitor. When detecting, on the basis of the result of consolidation, that one of each group of objects of monitor has malfunctioned, the consolidating unit notifies an associated monitor unit of the occurrence of one fault. When detecting that two or more objects of monitor have malfunctioned, the consolidating unit notifies the associated monitor unit of the occurrence of a plurality of faults. Each monitor unit is interconnected via a communicator thereof, and judges the states of objects of monitor by mutually transferring monitor data concerning its own system and monitor data concerning the other system. Owing to this configuration, the number of signal lines for use in notifying occurrence of malfunction to a monitor unit can be reduced. This leads to easy judgment of an abnormal state. A change in the number of objects of monitor can be coped with flexibly without the need of modifying the design of each monitor unit.

System for monitoring states of components of same kind incorporated

In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer, thereby completing the write instruction. Prior to executing a read instruction subsequent to the write instruction, the write address and the write data of the output buffer are transferred to a sync buffer and are stored into a write address holding register and a write data holding register. Further, a using state display register is set into the holding state. When the CPU executes the read instruction, the write data of the write data holding register is written into the memory mapped register and the end of the writing operation is synchronized with the end of the read instruction. When the sync buffer unit receives an interruption instruction in the holding state, an interruption return instruction address is returned to an address of the write instruction of the data in the holding state. The process is restarted from the write instruction of the memory mapped register by the control program by the end of the interruption.

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Kawasaki, Japan

Shoji Temma