Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Floadia Corporation

Hitachi, Ltd. & Engineering Corp.

Hitachi Vlsi

Shoji Shukuri

Yasuhiro Taniguchi

Mitsuru Hiraki

Kenichi Kuroda

Kazuhiro Komori

Kousuke Okuyama

Katsuhiko Kubota

Kazumasa Yanagisawa

Norio Suzuki

Takashi Hashimoto

Shuji Ikeda

Hitoshi Kume

Masataka Kato

Hiroyuki Uchiyama

Tetsuo Adachi

Yasuo Wada

Atsushi Ogishima

Masao Tamura

Koichiro Ishibashi

Masakazu Aoki

Masanao Yamaoka

Masataka Minami

Junichi Nishimoto

Hiroshi Yamaguchi

Tohru Ishitani

Shinichiro Kimura

Atsuo Watanabe

Masahiro Moniwa

Takahiro Nagano

Shinichi Minami

Shinji Sakano

Kazushige Sato

Koji Ishida

Tsutomu Okazaki

Eiji Takeda

Fumikazu Itoh

Keiya Saito

Takashi Nishida

Mitsuru Hirao

Dai Hisamoto

Tsuneo Ichiguchi

Yasunari Umemoto

Digh Hisamoto

Toshiaki Yamanaka

Nozomu Matsuzaki

Hideyuki Matsuoka

Natsuki Yokoyama

Hiromasa Noda

Kazuyoshi Shiba

Daisuke Okada

Takehisa Hayashi

Kiichi Ueyanagi

Eiichi Murakami

Yoshiaki Kamigaki

Yoshifumi Kawamoto

Takahiko Kato

Hideo Sunami

Toru Kaga

Yoshihisa Fujisaki

Toshikazu Nishino

Nobuyoshi Natsuaki

Toshiaki Nishimoto

Masaaki Terasawa

Kazunori Tsujimoto

Noboru Masuda

Masanobu Miyao

Toshifumi Takeda

Kazuyoshi Torii

Naoki Yada

Kazunori Furusawa

Yutaka Misawa

Kosuke Okuyama

Eiichi Ishikawa

Yoshihiro Ikeda

Terunori Warabisako

Kazuhiko Sagara

Kiyonori Ohyu

Nobuo Kotera

Hirotoshi Tanaka

Norikazu Hashimoto

Tatsuya Fukumura

Koji Kishi

Tadashi Suzuki

Yuuichi Madokoro

Toshiyuki Yoshimura

Keiichi Haraguchi

Keisuke Tsukamoto

Hidefumi Mukohda

Yasunori Ikeda

Hidenori Takada

Nobutoshi Matsunaga

Hideo Tobe

The present invention provides a solid-state imaging device and a camera system capable of recording a still image without using a recording medium. Each pixel P of an image sensor is provided with a photodiode, a transfer transistor, a reset transistor, and an amplifying transistor, as well as a memory element that has functions of a select transistor. The memory element has a structure integrating a drain side select transistor, a source side select transistor, and a memory transistor. By applying a program voltage to a memory gate electrode as a gate voltage, the memory transistor stores charge of an amount corresponding to an amount of light received by the photodiode in a charge storage layer.

Solid-state imaging device and camera system

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

Semiconductor integrated circuit device and a method of manufacturing the same

Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

A semiconductor device having plural memory cell regions featuring nonvolatile memory cells, each nonvolatile memory cell including a first insulating film formed over a semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, wherein each of the nonvolatile memory cells of a first memory cell region and each of the nonvolatile memory cells of a second memory cell region are formed adjacent to one another such that a drain region is shared between them.

A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.

A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. The second insulating film may be a laminated multi-layered insulator featuring a non-conductive charge trap film as an intermediate layer therein which is made of a silicon nitride film.

Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.

A method of manufacturing a semiconductor integrated circuit device is provided including providing a substrate with projecting island regions formed in stripes, with first regions of the substrate adjacent the projecting island regions and with a conductive film covering the projecting island regions and first regions. An insulating film is formed between the projecting island regions and conductive film, wherein the projecting island regions extend in a first direction in stripes. The conductive film is anisotropically etched using a mask covering portions of the conductive film to form conductive lines on sides of the projecting island regions and the portions of the conductive film integrated with the conductive lines, which conductive lines serve as common gate electrodes for MISFETs.

Semiconductor integrated circuit device and its manufacturing method

A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

Semiconductor integrated circuit device having deposited layer for gate insulation

Growing community of inventors

Koganei, Japan

Shoji Shukuri