Kabushiki Kaisha Toshiba

Shoji Seta

Naofumi Nakamura

Makoto Sekine

Hideaki Ikuma

Hideo Ichinose

Katsuya Okumura

Akihiro Kojima

Ichiro Mizushima

Yukihito Oowaki

Nobuo Hayasaka

Tokuhisa Ohiwa

Tsukasa Azuma

Takaya Matsushita

Junko Ohuchi

Hideo Shinomiya

Takeshi Yoshimoto

Yojiro Hamasaki

A solid-state imaging device according to an embodiment is a solid-state imaging device in which a plurality of pixel regions are formed into a two-dimensional array isolating the pixel regions from each other by element isolation regions, including a plurality of microlenses, a plurality of color filters arranged below the plurality of microlenses, a plurality of photoelectrical conversion sections arranged below the plurality of color filters and a magnetic field generating section provided on the element isolation regions between the plurality of microlenses and the plurality of photoelectrical conversion sections.

Solid-state imaging apparatus

A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device.

Solid-state imaging device

A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer.

Semiconductor device

A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.

Semiconductor device and wafer

A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. A plurality of first pad electrodes among the plurality of pad electrodes are arranged on an outer circumference of the semiconductor substrate to be along a first side of the semiconductor substrate, a plurality of first ball electrodes among the plurality of ball electrodes are arranged on an outer circumference of the rewiring layer to be along the first side, and any one of the plurality of first ball electrodes is connected to the first pad electrode positioned below the corresponding ball electrode through the contact wiring lines, and the first pad electrodes are not disposed on the lower side of the first ball electrodes positioned at an end of the first side.

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

Semiconductor device and method of designing a wiring of a semiconductor device

A semiconductor device includes: an LCD controller configured to output a plurality of image signals in parallel; a plurality of signal lines respectively corresponding to the plurality of image signals to be outputted in parallel; a plurality of terminal portions respectively connected to the plurality of signal lines; and delay circuits configured to delay a plurality of image signals, which are divided into a plurality of groups to the extent that the sum of each value of a current flowing through each signal line does not exceed a predetermined current value and outputted from a plurality of terminal portions, by a predetermined delay time from each other among the plurality of groups.

Semiconductor device and display device

A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a next routing module configured to set a second grid area and a second diagonal grid area and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire.

Semiconductor integrated circuit including a multi-level interconnect with a diagonal wire

A programmable logic device unit, a non-volatile memory unit which stores data for programming the programmable logic device unit in a part of data storage area thereof and a control circuit which controls the non-volatile memory unit to allow the data stored in a part of the data storage area to be read at power-on time and supplied to the programmable logic device unit are integrally provided on a semiconductor chip. Based on the program data, the programmable logic device unit forms an interface for allowing the non-volatile memory unit to operate as at least one of a register, a flash memory, a random access memory, and a read-only memory.

Semiconductor integrated circuit device

Computer automated design system, a computer automated design method, and a semiconductor integrated circuit

Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.

Semiconductor device and manufacturing method of the same

A dry etching method comprises sequentially laminating a first insulating layer containing carbon and a second insulating layer containing carbon on a substrate, patterning the second insulating layer to form a mask; forming grooves in the first insulating layer by etching the first insulating layer with the second insulating layer used as a mask such that each of the grooves has a side surface and a bottom surface in the first insulating layer; and removing the second insulating layer by use of a reactive gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms.

Dry etching method and semiconductor device manufacturing method

According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

High precision pattern forming method of manufacturing a semiconductor device

Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the metal film, and performing a plurality of etching works to the insulating film or the metal film in conformity with the various kinds of mask.

Growing community of inventors

Yokohama, Japan

Shoji Seta