Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matushita Electric Industrial Co., Ltd.

Shoji Sakamoto

Kiyoto Ohta

Tomonori Fujimoto

Hiroyuki Sadakata

Yuji Yamasaki

Hidefumi Otsuka

Yoshifumi Fukushima

Koichiro Nomura

A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.

Semiconductor integrated circuit

Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

Semiconductor memory test device

In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is &ldquo;L&rdquo;, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.

Semiconductor device having integrated memory and logic

For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed system LSI, a test data, an address and a memory control signal required for the test of the memory are generated using the divided-frequency output signal of an address generator, i.e., frequency-divider of an external clock, and a mixer circuit for periodically inverting a pass/fail signal as the test result is provided. This enables the test of the memory with a total of 2 pins of input and output in all. Thus, it becomes possible to test the memory and the logic circuit simultaneously at the time of burn-in test thereof.

Growing community of inventors

Kyoto, Japan

Shoji Sakamoto