Seiko Instruments Inc

Other

Ablic Inc.

Shoji Nakanishi

Tomomitsu Risaki

Koichi Shimazaki

Yoshikazu Kojima

Kazutoshi Ishii

Naoto Inoue

Yasuhiro Moya

Kiyoaki Kadoi

Kentaro Kuhara

Takao Akiba

Koushi Maemura

Yutaka Hayashi

Hitomi Sakurai

Sumitaka Goto

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Semiconductor device and ball bonder

A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

Semiconductor device and manufacturing method therefor

Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n&#xb1; layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Semiconductor device

A floating non-volatile memory has a substrate and source and drain regions disposed in a surface region of the substrate and spaced apart from each other with a channel forming semiconductor region disposed therebetween. A gate insulating film is disposed on the channel forming semiconductor region. A single crystal control region is disposed in the surface region of the substrate and is electrically separated from the channel forming semiconductor region. A control gate insulating film is disposed on the single crystal control region. A floating gate is disposed on the control gate insulating film and is capacitively coupled with the single crystal control region. A chemical-vapor-deposited shield insulating film is formed in a gas atmosphere charge-balanced on the floating gate. A shield conductive film is disposed on the chemical-vapor-deposited shield insulating film and capacitively coupled with the floating gate.

Floating gate non-volatile memory

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Semiconductor integrated circuit and manufacturing method therefore

Semiconductor dicing and assembling method

In a MOS transistor or memory cell that uses a thin oxide film as a gate insulation film, ion-implantation-induced damage protection films (mask oxide films) are formed on side walls of a polysilicon gate electrode to minimize flaws in the structure of the thin oxide film right under the polysilicon gate electrode edge, which are induced by the ion implantation performed during the process of forming self-aligned source and drain regions.

Method of making semiconductor devices having an implant damage

A method of concurrently forming thick and thin field silicon oxide films for use as element separation on the silicon substrate. An under-layer silicon oxide film is formed over the silicon substrate. A silicon nitride film is chemically-vapor-deposited over the under-layer silicon oxide film. The silicon nitride film is selectively etched to expose the under-layer silicon oxide film to thereby form openings. The silicon substrate is annealed within a heated atmosphere of ammonia gas to convert a surface portion of the exposed under-layer silicon oxide film into a thermally nitrified silicon oxide film within the openings. The thermally nitrified silicon oxide film is selectively removed from some of the openings and maintained in the other openings. The silicon substrate is thermally oxidized through the openings to concurrently form relatively thick field oxide film within said some of the openings and relatively thin field oxide film within the other openings.

Growing community of inventors

Chiba, Japan

Shoji Nakanishi