Denso Corporation

Nippondenso Co., Ltd.

Shoji Miura

Makio Iida

Toshio Sakakibara

Takayuki Sugisaka

Takanori Teshima

Naohiko Hirano

Mikimasa Suzuki

Akira Kuroyanagi

Satoshi Shiraki

Yoshimi Nakase

Chikage Noritake

Akihiro Niimi

Atsushi Komura

Hiroyuki Ban

Yutaka Fukuda

Yoshitsugu Sakamoto

Kenji Kondo

Yoshihiko Isobe

Nobuyuki Kato

Kimiharu Kayukawa

Akira Tanahashi

Yoshikazu Sakano

Tetsuaki Kamiya

Osamu Ishihara

Fuminari Suzuki

Keiichi Kon

Tetsuhiko Sanbei

Mitsuhiro Saitou

Takeshi Miyajima

Tomoatsu Makino

Nobumasa Ueda

Takashi Nakano

Yutaka Tomatsu

Kiyoshi Yamamoto

Yoshiaki Nakayama

Makoto Ohkawa

Ichiharu Kondo

Takashi Suzuki

Tadashi Shibata

Hajime Soga

Noriyuki Iwamori

Tadashi Suzuki

Masami Saito

Akitaka Murata

Keiji Shinyama

Yoshitaka Nakano

Katsuyoshi Oda

Kanemitsu Terada

Keizou Kajiura

A semiconductor device includes: a semiconductor substrate; a base member; a tin-based solder layer; a first metal layer; and a first alloy layer. The semiconductor substrate is bonded to the base member through the first metal layer, the first alloy layer and the tin-based solder layer in this order. The first alloy layer is made of a first metal in the first metal layer and tin in the tin-based solder layer. The first metal layer is made of at least one of material selected from the group consisting of titanium, aluminum, iron, molybdenum, chromium, vanadium and iron-nickel-chromium alloy.

Semiconductor device having tin-based solder layer and method for manufacturing the same

A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a conductive layer and a connecting member. The method includes: forming the semiconductor part on a semiconductor substrate so that a cell portion is provided; forming the conductive layer on the substrate; forming a first resist layer to cover a part of the conductive layer corresponding to the cell portion; etching the conductive layer with the first resist layer as a mask so that a first conductive layer is provided; removing the first resist layer and forming a second conductive layer to cover a surface and an edge of the first conductive layer. The second conductive layer has a Young's modulus equal to or larger than the semiconductor substrate.

Method for manufacturing mold type semiconductor device

A power element package includes a semiconductor chip, radiating members, a mold resin member, a lead terminal for control signals, and lead terminals for large electric current. On a heat accepting surface of the radiating member, an insulating layer and a conductive layer are disposed. The lead terminal for control signals is electrically connected with a gate of the semiconductor chip through the conductive layer. An emitter of the semiconductor chip is electrically connected through a solder connection member with a non-insulating portion of the heat accepting surface.

Molded semiconductor device with heat conducting members

A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Mold type semiconductor device

A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

Power MOS transistor having capability for setting substrate potential independently of source potential

A semiconductor device includes a semiconductor substrate; an aluminum electrode disposed on the substrate; a protection film disposed on the aluminum electrode; an opening disposed on the protection film for exposing the aluminum electrode; and a metal electrode disposed on a surface of the aluminum electrode through the opening. The aluminum electrode includes a concavity disposed under the opening. The aluminum electrode disposed at the concavity has a thickness equal to or larger than a depth of the concavity. The surface of the aluminum electrode includes multiple concavities and multiple convexities.

Semiconductor device having aluminum and metal electrodes and method for manufacturing the same

A package type semiconductor device comprising: a semiconductor chip having a semiconductor part; a main electrode for connecting to a first region of the semiconductor part; a control wiring layer for connecting to a second region of the semiconductor part; a blocking member electrically isolated from the control wiring layer; a first metallic layer; a protection film disposed among the main electrode, the control wiring layer and the blocking member; and a metal block for connecting to the main electrode through the first metallic layer. The chip, the main electrode, the control wiring layer, the blocking member, and the metal block are packaged. The blocking member is disposed between the main electrode and the control wiring layer.

Package type semiconductor device

A drift layer is formed on a substrate. A base region is formed on the drift layer. A plurality of source regions are formed in a surficial layer of the base region. A plurality of gate electrodes face to the base region and the source region via a gate insulating film. A source electrode is brought into contact with the base region and the source region. A nitrogen cluster containing layer is embedded in the drift layer so as to extend laterally under the base region so that at least part of the drift region is left under the nitrogen cluster containing layer.

Metal oxide semiconductor transistor having a nitrogen cluster containing layer embedded in the substrate

In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and nsource regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each nsource region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.

Semiconductor device

A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.

Method for manufacturing semiconductor device having controlled surface roughness

A semiconductor device includes a semiconductor chip, a first heat sink, a second heat sink, and a mold resin. The first heat sink is electrically and thermally connected to a surface of the semiconductor chip for functioning as an electrode for the semiconductor chip and releasing the heat generated by the semiconductor chip. The second heat sink is electrically and thermally connected to another surface of the semiconductor chip for functioning as another electrode for the semiconductor chip and releasing the heat. The semiconductor chip and the first and second heat sinks are covered with the mold resin such that the heat sinks are exposed on a substantially flat surface of the mold resin.

Molded semiconductor power device having heat sinks exposed on one surface

A load drive circuit, disposed to drive an inductive load, includes a reflux closed circuit connected to the load. A flywheel diode is placed in the reflux closed circuit. A MOS transistor, disposed to turn on/off current to drive the load, is connected in parallel to the flywheel diode. A capacitor is disposed to connect its both ends to a gate and a drain of the MOS transistor, while a resistor is disposed to connect its both ends to the gate and a source of the MOS transistor. During a recovery operation of the flywheel diode, with the help of the capacitor and resistor, a gate-to-source voltage of the MOS transistor is pulled up to a value over a threshold for a predetermined period of time. Pulling up the gate-to-source voltage results in a softened recovery characteristic of the flywheel diode, suppressing recovery surges.

Load drive circuit using flywheel diode

A semiconductor device has a semiconductor substrate, several cell blocks provided on the semiconductor substrate, several gate electrodes electrically independent of one another and respectively provided in the cell blocks, and several gate pads respectively connected with the gate electrodes. In this construction, the cell blocks can be determined whether they are defective or not by utilizing the gate pads easily. Therefore, the semiconductor device can be operated only with non-defective cell blocks.

Semiconductor device and method for manufacturing the same

A semiconductor wafer in which black silicon does not form during trench etching even when side rinsing is carried out during a photolithography process. In an embedded oxide film interposed between first and second semiconductor wafers of a bonded SOI wafer, the film thickness of a peripheral part thereof is made greater than a predetermined thickness Dsio so that it functions as an oxide film for etching prevention. When side rinsing is carried out in a resist coating process to form an opening in an oxide film for masking use in trench etching, the oxide film for masking use at the periphery is also etched during formation of the opening. Due to over-etching at that time, the oxide film for etching prevention is etched by a film thickness d,. During trench etching also, the oxide film for etching prevention is etched by a film thickness d,. Accordingly, if the film thickness Dsio of the oxide film for etching prevention is set to be greater than the film thickness d,&plus;d,, because an oxide film remains at the final stage, the formation of black silicon can be prevented.

Method for etching trench in manufacturing semiconductor devices

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Nukata-gun, Japan

Shoji Miura