Matsushita Electric Industrial Co., Ltd.

Shoji Marukawa

Yoshimasa Oda

Toshinori Okamoto

Takashige Hiratsuka

Shinichiro Sato

Yoichi Ogura

A digital data reproducing apparatus includes, a read head for reading data from a recording medium, an analog-to-digital converter for converting the data read by the read head into digital data, a memory for storing the digital data converted by the analog-to-digital converter, a phase control circuit for controlling phase of the digital data, and off-track detector for detecting off-track of the read head from a track on the recording medium. In the apparatus, storing operation to the memory is controlled based on output signal from the off-track detector and output signal from the phase control circuit.

Digital data reproducing apparatus

A digital signal processing apparatus for reading out a signal from a recording medium of a digital recording apparatus of high-frequency cutoff type is provided which includes: a read head for reading out the recorded signal from the recording medium a low-pass filter for removing high frequency noise from the output signal of the read head an analog/digital converter for converting the analog reproduced signal filtered by the low-pass filter to a digital reproduced signal; an FIR filter for filtering the digital reproduced signal with the use of an adaptive equalization coefficient so that the frequency response of the signal is equalized with the partial response which has a frequency characteristic suited for reading the reproduced signal; an adaptive equalization coefficient setting device and a partial response temporal judgment device for determining the adaptive equalization coefficient; and a Viterbi decoder for decoding a partial response equalized data released from the FIR filter to a data for judgment.

Apparatus for processing a reproduced digital signal

Digital reproduced signal processing device

A tracking error detecting apparatus converts photoelectric current obtained by a photo detector into voltage signals at current/voltage conversion circuits, and adds the voltage signals to generate two signal series at adders. The two signal series are digitalized at analog to digital converters, are subjected to interpolation processing at interpolation filters and have their zero cross points detected by zero cross point detector circuits respectively. A phase difference between the zero cross points of the two signal series is detected by a phase difference detector circuit, and the phase difference is subjected to band restriction by a low pass filter, thereby to obtain a tracking error signal. The tracking error detecting apparatus is capable of coping with speed doubling of an optical recording/reproducing apparatus and density enhancing of an optical recording medium with a small size and at low cost.

Tracking error detection device

A clock generation circuit of the present invention extracts a phase error signal of a digital signal obtained from a recording medium ( ) by a phase comparator ( ), filters the phase error signal by a loop filter ( ). In a first embodiment it converts the signal into an analog signal by a minute control D/A converter ( ), detects whether the signal is within a set range by a range detector ( ), generates a modulation reference signal by a modulation reference signal generator ( ), modulates the modulation reference signal by a pulse width modulator ( ), adds a frequency set value and the modulation reference signal by an adder ( ), converts the addition result into an analog signal by a rough control D/A converter ( ), cuts high-band components of the analog signal by a low-pass filter ( ), adds the analog signals output from the minute control D/A converter ( ) and the low-pass filter ( ) by an analog adder ( ), and outputs a clock signal by a voltage controlled oscillator ( ) on the basis of an output signal of the analog adder ( ). Thereby, a clock signal which can continuously lock a wide frequency range can be generated. In a second embodiment the loop filter output is oversampled ( ), then interpolated ( ) and modulated by a multivalued delta sigma modulator.

Wide frequency range PLL clock generating circuit with delta sigma modulating circuitry for reducing the time changing ratio of the input voltage of a voltage controlled oscillator

When a playback signal of recorded data which is a DC free code has non-linearity, the playback signal is equalized by a waveform equalization unit, and sampled by an analog-to-digital converter. The sample data is binarized, and an offset amount is detected by utilizing the feature of the DC free code, and then the reference level of the analog-to-digital converter is controlled so that the output of a first integrator becomes 0. Thereafter, the output of a level shift circuit is input to a second integrator, and the level shift amount is controlled so that the output becomes 0. The converged value is retained. After this learning, by using the retained level shift amount, the reference level is controlled so that the output of the second integrator becomes 0, thereby performing speedy and accurate DC offset control.

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Ehime, Japan

Shoji Marukawa