Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Shoji Ariizumi

Makoto Segawa

Fujio Masuoka

Taira Iwase

Hiroshi Iwahashi

Youichi Suzuki

Shigeto Mizukami

Takeo Kondo

Hisaaki Maiwa

Seishi Okamoto

A semiconductor memory device including: a semiconductor substrate of a first conductivity type; triple-layer gate electrode structure formed on the semiconductor substrate and having first insulating film and second insulating film on upper and lower sides of the electrode; a pair of first impurity regions of a second conductivity type in the semiconductor substrate for contacting an opposite side face of the gate electrode structure; an impurity region selectively formed in a channel region corresponding to the data to be fixed in the memory device; an insulating wall on a portion of at least one side face of the gate electrode structure; a pair of second impurity regions of the second conductivity type in the substrate, each of the second regions overlapping with a corresponding one of the first impurity regions for contacting an opposite side face of the insulating wall; a contact pad layer connected to one of the second impurity regions for covering at least a portion of the first insulating film; and a wiring layer connected to the contact pad layer.

Semiconductor memory device and method of manufacturing it

A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Semiconductor device

A semiconductor memory device is formed of a polycrystalline silicon electrode terminal layer, which is formed on a MOS transistor except over the gate region and is connected to the drain region of the MOS transistor, and metal wire layer, which is formed on the MOS transistor except over the gate region and is connected to the electrode terminal layer to transmit output signals. Data is written into the semiconductor memory device by ion implantation of the gate of the MOS transistor after the metal wire layer is formed.

Method of manufacturing a read only semiconductor memory device

This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Protected MOS transistor circuit

A read only memory contains a conductive layer of polysilicon which contacts the drains of memory cell MOS transistors and lies near and on a gate electrode. A data line made of aluminum and the drain of the MOS transistors are interconnected through the conductive layer. A method of manufacturing the ROM such structure is also disclosed.

Method of making a semiconductor ROM device

A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripheral circuit for driving the memory cell array is formed in at least one second well region of the opposite conductivity type formed separately from the first well region in the surface area of the semiconductor body. The second well region is set at a bias level deeper than the first well region.

Random access memory with resistance to crystal lattice memory errors

A semiconductor read only memory device is disclosed, which comprises a plurality of memory cells each including drain and source regions separately formed on a semiconductor substrate of p-conductivity type and a gate electrode insulatively disposed over the semiconductor substrate and extending between the drain and source regions. A poly-silicon layer containing an impurity of the p-conductivity type is formed such that it is contiguous to each drain region. A silicon nitride mask having electric insulation property and antioxidation property is formed selectively on the poly-silicon layer. The poly-silicon layer is oxidized selectively except for portions contiguous to the drain regions in the presence of the silicon nitride masks. An aluminum layer is selectively made in contact with the poly-silicon layer depending on the presence or absence of the silicon nitride layer.

Semiconductor read only memory device with selectively present mask layer

A MOSFET read only memory is disclosed. A silicon material directly contacts a drain of a memory cell transistor formed in a silicon substrate to obtain a low contact resistance. A drain electrode layer partially covers two oxide films which are above a gate electrode, to increase a contact area between a metal wiring layer constituting an output line and the drain electrode layer.

Read only memory

Read only memory semiconductor device

A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

MOSFET buffer circuit with an improved bootstrapping circuit

A semiconductor device having a pair of wiring layers connected in parallel with each other in which a first wiring layer is formed over a semiconductor substrate through a insulation layer. The first wiring layer is made of poly-Si and has relatively high resistivity. Therefore a second wiring layer is formed over the first wiring layer through an insulation layer. A portion of the second wiring layer has low conductivity and is parallel connected to the first wiring layer in order to reduce the resistivity of the wiring layer. Another portion of the second wiring layer has low conductivity and is used as resistive means.

Semiconductor device having multiple conductive layers and the method of

Read only semiconductor memory device with polysilicon drain extensions

A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

Redundancy circuit for a semiconductor memory device

An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply. The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line.

Inverter circuit provided with gate protection

A semiconductor memory device is disclosed in which, when a main memory contains an error bit cell, the main memory is switched to an auxiliary memory by cutting off an interconnection wire between a decoder and the main memory, and subjecting a high resistance polysilicon connected between the decoder and the auxiliary memory to laser annealing to reduce the resistance of the high resistance polysilicon and to connect the decoder and the auxiliary memory.

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Tokyo, Japan

Shoji Ariizumi