Kawasaki Microelectronics, Inc.

Megachips Corporation

Shoichiro Kashiwakura

A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.

Phase comparison device and DLL circuit

Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order.

Parallel to serial conversion apparatus and method of converting parallel data having different widths

A communication system for transmitting and receiving data at high speed can be self-tested at actual operating speed with low cost, and without increasing the chip area. A test signal generation unit generates test parallel data. A transmitter for test purpose converts the parallel data into serial data. A selector selectively supplies the serial data output from the transmitter to a receiver during a test operation. The receiver converts the serial data into parallel data. After that, a detector detects an error in the parallel data output from the receiver. In this case, only the transmitter is disposed in correspondence with receivers. Serial data output from the transmitters is supplied to the receivers through the selector.

Growing community of inventors

Chiba, Japan

Shoichiro Kashiwakura