Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Kioxia Corporation

Hitachi Microcomputer Engineering, Ltd.

Shoichi Watanabe

Mitsuhiro Noguchi

Takashi Nakajima

Satoshi Nagashima

Tadashi Iguchi

Kenji Gomikawa

Terumine Hayashi

Kenichi Yoshioka

Tetsuroo Honmura

Karin Takayama

Shotaro Murata

Ishi Mitsuhashi

Kazunari Toyonaga

Hiroyuki Kuroe

Kenzo Goto

Takashi Natabe

Takayuki Takei

According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WTdisposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.

Semiconductor memory device capable of suppressing leakage current

A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.

Nonvolatile semiconductor memory device comprising memory gate and peripheral gate having different thicknesses

A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.

Semiconductor device and semiconductor device manufacturing method

A method of controlling the criticality of a nuclear fuel cycle facility includes steps of producing a reactor fuel by adding less than 0.1% by weight of gadolinia to a uranium dioxide powder with a uranium enrichment of greater than 5% by weight and controlling the effective neutron multiplication factor of a uranium dioxide system in a step of handling the reactor fuel to be less than or equal to the maximum of the effective neutron multiplication factor of a uranium dioxide system with a uranium enrichment of 5% by weight.

Method of controlling criticality of nuclear fuel cycle facility, method of producing uranium dioxide powder, reactor fuel rod, and fuel assembly

A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.

Nonvolatile semiconductor memory

A nonvolatile semiconductor storage device includes a semiconductor substrate, and at least one memory cell formed on the semiconductor substrate, the at least one memory cell having a gate electrode unit in which a floating gate electrode and a control gate electrode are stacked, at least part of the control gate electrode being silicidated. The nonvolatile semiconductor storage device further includes at least one dummy transistor formed on the semiconductor substrate, the at least one dummy transistor having a first dummy electrode, and a second dummy electrode which has a current leakage path and which is stacked on the first dummy electrode.

Nonvolatile semiconductor storage device having silicide in control gate electrode

A method of extracting timing characteristics from transistor circuit data of modularity design products (a module) such as a CPU core in which the extracted timing characteristics are used for the timing verification of a circuit including a module to be extracted and timing constraints when logical synthesis or timing-driven layout is made. Particularly, since conditions fit for a timing rule of the module are included in timing characteristics when timing verification is executed by simulation, verification free of pseudo error is enabled. Also, the configuration of a timing characteristic library, a storage medium storing it and an LSI designing method using the storage medium are provided.

Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, LSI designing method, and gate extraction method

A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.

Growing community of inventors

Kawasaki, Japan

Shoichi Watanabe