Fanuc Corporation

Fujitsu Fanuc Limited

Shoichi Otsuka

Mitsuo Kurakake

Yutaka Muraoka

Hideo Miyashita

Hajimu Inaba

Nobuyuki Kiya

Yoshiaki Ikeda

Numerical control device for transfer machines

Interrupt control circuit for multi-master bus

A picture processing apparatus inputs window data (W) to look-up tables (TBL) in which operators (G or F) to be applied to pixel data (x) are stored in correlation to the locations of the pixel data. By switching between the operators (G or F) contained in the look-up tables (TBL), window processing corresponding to a data address (i,j) is performed on input pixel data (x.sub.ij).

Picture processing apparatus including data conversion table for

Apparatus for convolution picture processing using delay and

Picture processing apparatus including a dual port memory

Picture processing apparatus

A system for coupling a visual sensor processor (B) and a robot controller (A), so that the processing of the whole system is sped up and the configuration of the system is low-cost. To this end, the visual sensor processor (B) and the robot controller (A) are coupled together via a bidirectional high-speed data transfer channel (10, 28, l.sub.1, l.sub.2) for an exchange therebetween of required information. A nonvolatile memory (6) and a serial interface (12) for connection to an external input/output device, are installed in the robot controller (A), and are shared by the visual sensor processor (B) and the robot controller (A) through utilization of the channel.

System for coupling a visual sensor processor and a robot controller

Picture introducing apparatus

Spatial product sum calculating unit

Industrial robot having a function for controlling a current of a motor

A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines the priority of the microprocessors. According to the system of the present invention, it has a common memory that is selectively connected to the buses, data is transmitted without affecting the operation of the microprocessors on the receiving side, data transfer between the microprocessors having different cycle times is carried out at speeds that are adapted to the cycle times of the individual microprocessors, and the degree of the exclusive use of the bus by the microprocessor is prevented from being reduced when the direct memory access transfer is carried out. Consequently, a system for controlling a plurality of microprocessors having an improved performance is obtained in accordance with the present invention.

System for controlling a plurality of microprocessors

Growing community of inventors

Hino, Japan

Shoichi Otsuka