Fujitsu Corporation

Fujitisu Limited

Shoichi Kawamura

Masaru Yano

Kenji Nagai

Makoto Niimi

Hirokazu Nagashima

The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

AC sensing method memory circuit

In a block which is a target of detection of flag data, a page buffer reads data of memory cells of each memory cell by block unit, and latches the data. A detection circuit performs detection of the flag data for each block based on output of the page buffers of one block.

Nonvolatile semiconductor memory device, nonvolatile semiconductor memory device-integrated system, and defective block detecting method

First and second memory units store reference values and verification values for generating reference voltages and verification voltages of nonvolatile multilevel memory cells. A reference voltage generator generates the reference voltages and the verification voltages according to the reference values and the verification values stored in the first and second memory units. Since the first and second memory units are rewritable, the reference voltages and the verification voltages can be set after the fabrication of the cell memory in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process. A programming test circuit for obtaining the reference voltages and the verification voltages can also be used to set the reference voltages and the verification voltages after the fabrication of the cell memory. Consequently, it is possible to improve the read margins of data read from the memory cells with an enhancement in fabrication yield.

Nonvolatile multilevel cell memory

A nonvolatile semiconductor memory with a plurality of banks in which copy back is performed between banks. An input circuit accepts input of a copy back command which requests a data transfer in the memory. When the copy back command is input from the input circuit, a judgment circuit judges whether a source and a destination are in the same bank. If the judgment circuit judges that the source and the destination are in the same bank, a first transfer circuit transfers data in the same bank. If the judgment circuit judges that the source and the destination are in different banks, a second transfer circuit transfers data between the two different banks.

Semiconductor memory

A memory cell array of a NAND-type flash memory is divided into a first and second cell arrays, and, during a read operation, a first voltage is applied to non-selected word lines of the first cell array, and a second voltage lower than the first voltage is applied, to non-selected word lines of the second cell array. The first cell array has a comparatively large write operation frequency, and therefore readily assumes an over-programmed state as a result of repeated write operations, whereas the second cell array has a comparatively small write operation frequency, and it is therefore difficult for same to assume an over-programmed state. As a result, the first voltage is made high, such that read problems are avoided even if over-programming arises, and the second voltage is made low, such that a read disturb is suppressed and a data change is avoided.

Read disturb alleviated flash memory

The invention is to provide a novel non-volatile memory capable of recording multi-bit data. The invention is a non-volatile memory which has: first and second source-drain regions SD , SD at the surface of a semiconductor substrate; and a non-conductive trapping gate TG, and a conductive control gate CG, formed on a channel region there between via an insulating film. Further, the non-volatile memory has a first or second state in which, by applying a voltage between the first and second source-drain regions SD , SD , hot electrons produced in the vicinity of the first or second source-drain region are locally captured in a first or second trapping gate region TSD , TSD in the vicinity of them; and, a third state in which, by applying a voltage between the control gate and the channel region, electrons (or charge) are (is) injected into the entire trapping gate. According to whether or not the above-mentioned third state is adopted, one-bit information can be recorded, and according to whether or not the first and second states are adopted, two-bit information can be recorded. Consequently, information totaling three bits can be recorded in a single memory cell.

Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate

The present invention provides a multi-bits non-volatile memory circuit having a cell transistor with non-conductive trap gate which has a cell array capable of reading a plural data simultaneously. The present invention is a non-volatile memory circuit in which a plurality of cell transistors M having a non-conductive trapping gate TG are arranged, comprising: a plurality of source-drain lines SDL, which are connected commonly with the source-drain regions SD SD of cell transistors adjacent in row direction, wherein these adjacent source-drain lines are set to a floating state F, a read-out voltage application state BL, a reference voltage state OV, a read-out voltage state BL, and a floating state F, and the source-drain lines SDL in the read-out voltage state is caused to function as bit lines, such that a plurality of data are read out simultaneously. The above states are generated by the page buffer P/B connected to the source-drain line. The data read and hold are performed by the page buffer.

Nonvolatile memory circuit for recording multiple bit information

The invention provides a NAND type nonvolatile memory comprising: a sense circuit,having a constant current supply source P,connected to a bit line to which memory cells are connected and a sense transistor N,for sensing potential at the connection point thereof; a first reference potential ARVss on the opposite side from the bit line of the memory cells; and a second reference potential PBVss to which the source of the sense transistor is connected, wherein during Erase-verify operations the first reference potential ARVss and the second reference potential PBVss are controlled to predetermined positive potential. By controlling the first reference potential ARVss to positive potential, the control gate level of a memory cell can be equivalently brought to Erase-verify level (which is negative), and by further controlling the second reference potential PBVss of the sense transistor N,to positive potential as well, the equivalent threshold voltage of the sense transistor N,can be increased, or the equivalent trip level of the sense inverter increased, thereby solving the conventional problems associated with Erase-verify operations.

NAND type nonvolatile memory with improved erase-verify operations

A non-volatile semiconductor memory device comprises a plurality of memory cell units each of which includes a plurality of non-volatile memory cells capable of having data electrically rewritten; a storage unit; and an access inhibiting circuit. The storage unit stores therein the defect information of the memory cell unit not normally operating. The access inhibiting circuit judges the condition of the memory cell unit within the device according to the defect information stored in the storage unit. Access to the memory cell unit not normally operating is inhibited in accordance with the result of the judgement. Since the device can control the information of the memory cell unit not normally operating by itself, users of the device need not manage the defective memory cell unit. Consequently, the usability of the device is enhanced and the cost of a system mounting the device is curtailed. Particularly, it is effective for the non-volatile semiconductor memory device for file allowing the presence of inoperative memory cells.

Non-volatile semiconductor memory device

A nonvolatile memory that has a plurality of floating gate type cell transistors comprises a read buffer circuit, connected to the bit line, that detects the threshold voltage states in the cell transistor. Each cell transistor can hold 2,threshold voltage states and accordingly, the read buffer circuit reads N bits of data. For this purpose, the read buffer circuit has a latch circuit that latches the read data in accordance with the detected threshold voltage state. This latch circuit has a first and second latch reversal circuit for reversing the latched state to the first or second state. When the read buffer circuit reads the first bit being held in the cell transistor, the latch circuit in its initial state is reversed or not reversed by the first latch reversal circuit in accordance with the detected first and second threshold voltage state, or third and fourth threshold voltage state, and that latch state is output as the first data. Furthermore, when the lower order second bit held in the cell transistor is read next, the read buffer circuit is reversed or not reversed from the latch state corresponding to the first data above by the first latch reversal circuit in accordance with the detected first or second threshold voltage state. Then, it is reversed or not reversed by the second latch reversal circuit in accordance with the detected third or fourth threshold voltage state and the latch state is output as the second data.

Nonvolatile memory for storing multivalue data

The present invention is a nonvolatile semiconductor memory having, in addition to a main storage region for storing ordinary data, a hidden storage region for storing a special code for preventing unauthorized copying, and this hidden storage region is in a read enabled state at the time of a write protected state, and is in a read prohibited state at a time when there is no write protected state. Therefore, a hidden storage region can be read out only after a semiconductor memory vendor stores a special code in a hidden storage region, and sets the hidden storage region to a write protected state. And the method for changing to this write protected state is a secret to everyone other than the vendor. As a result thereof, even if a semiconductor memory, for which a special code is not stored in a hidden storage region, is illegally obtained on the black market, since hidden storage region readout is still prohibited, illegally copied data cannot be used, consequently preventing unauthorized copying.

Nonvolatile semiconductor memory for preventing unauthorized copying

A nonvolatile semiconductor memory device has an array of memory cells in columns and rows, and has word lines and bit lines provided in orthogonal directions, the memory cells for each column sharing one of the bit lines, and the memory cells for each row sharing one of the word lines. The memory device includes a plurality of subblocks of N page buffers where N is a given positive integer, the N page buffers for each subblock temporarily storing data bits that are written to or erased from N memory cells at a time in the memory array in response to a selected one of the word lines. A verify/output circuit produces, in response to signals output by the plurality of subblocks of N page buffers, a verify status of each of the respective subblocks that indicates whether the data bits are properly written to or erased from the N memory cells, the verify/output circuit outputting the verify status of at least one of the plurality of subblocks to an external device.

Growing community of inventors

Kawasaki, Japan

Shoichi Kawamura