Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Shohei Michimoto

Taketo Heishi

Hajime Ogawa

Teruo Kawabata

Shuichi Takayama

Toshiyuki Sakata

Yasuhiro Yamamoto

Ryoko Miyachi

Tomoo Hamada

Hirotetsu Tomita

Kiyoshi Nakashima

Yukio Iimura

Kyoko Hattori

Kenji Hattori

A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

Compiler apparatus

A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.

Program converting apparatus and program conversion method

A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a 'if' conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

Compiler apparatus with flexible optimization

The present invention effectively utilizes auxiliary registers and provides a compiler system which secures error detectability when the auxiliary registers are shared for plural uses. The instruction definition resource configuring unit configures, as preparation for processing by the register assigning unit, respective resources such as a register to be defined or referred to by for each instruction in an intermediate code. The instruction definition resource configuring unit detects possibility of instructions each of which is to be decomposed into plural instructions. As for an instruction to be possibly decomposed, the instruction definition resource configuring unit configures a corresponding register in the intermediate code, assuming the corresponding register used for the decomposition to be defined and referred. The register assigning unit uses the register as a general register as far as a live range of the register used for the decomposition does not overlap.

Compiling apparatus

A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.

Compiler apparatus and linker apparatus

A compiler, which is a compiler that realizes program development in a fewer man hours, translates a source programwritten in a high-level language into a machine language program. This compileris comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unitthat parses the source program; an intermediate code conversion unitthat converts the source programinto intermediate codes based on a result of the parsing performed by the parser unit; an optimization unitthat optimizes the intermediate codes according to the directive; and a code generation unitthat converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

Compiler apparatus for optimizing high-level language programs using directives

A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.

Computer system, compiler apparatus, and operating system

A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unitanalyzing syntax of source program, an intermediate code converting unitconverting the syntactically analyzed source programto an intermediate code and code generating unitconverting the intermediate code to the RTL description. The intermediate code converting unitincludes a detecting unitdetecting a particular hardware defined in the header fileout of the source programand a replacing unitreplacing the detected particular hardware in the detecting unitwith the intermediate code corresponding to a particular hardware.

Compiler

A compiling unit () generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit () generates an appropriate direct addressing branch instruction by judging whether an instruction set used at a branch source and an instruction set used at a branch destination are the same. Also, one reference instruction set is determined. The compiling unit () adds a mode adjusting instruction that belongs to the reference instruction set and that is for causing a branch to an instruction placed at a branch destination and for selecting the instruction set that is originally to be selected. The mode adjusting instruction provides an alternative branch destination corresponding to an original branch destination, and the compiling unit () generates an indirect addressing branch instruction for causing a branch to the alternative branch destination and for selecting the reference instruction set.

Program conversion apparatus, program conversion method, and computer program for executing program conversion process

Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n&#x2266;2). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.

Growing community of inventors

Takatsuki, Japan

Shohei Michimoto