Nec Corporation

Other

Real World Computing Partnership

Shogo Nakaya

Naoya Henmi

Tomoki Saito

A reconfigurable circuit () according to the present invention includes: a switching element group that is formed by a plurality of switching elements (), an ON state and an OFF state of the switching element being rewritable in accordance with a resistive state; and a configuration controller () that senses the resistive state of each of the switching elements and programs each switching element, wherein the configuration controller () senses the resistive state of each switching element () by applying an inspection-purpose voltage across the opposite electrodes of the switching element (), and when the sensed resistive state is abnormal, the configuration controller applies a programming voltage across the opposite electrodes of the switching element such that the resistive state of the switching element becomes the programmed resistive state.

Reconfigurable circuit and method for refreshing reconfigurable circuit

Bidirectional bufferD includes: multiplexerthat is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate bufferthat is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexeras input; demultiplexerthat receives the output of tristate bufferas input; programming transistor trwhose drain terminal is connected to the input terminal of tristate bufferand programming transistor trwhose drain terminal is connected to the output terminal of tristate bufferInput terminals iand iof multiplexerare connected to respective output terminals tand tof demultiplexer

Bidirectional buffer and control method thereof

A radio tag sensor system includes a plurality of radio tag sensor chips, which incorporate respective sensors, store unique identification numbers, a plurality of micro base stations, and a central processing unit which perform communications with the micro base stations via a connection network. Each of the micro base stations performs wireless communications with and wirelessly supplies electric power to only those of the radio tag sensor chips which are disposed in an assigned region thereof. Each of the assigned regions includes at least one radio tag sensor chip which is not included in the other assigned regions. The central processing unit controls the communications via the connection network. The central processing unit collects the sensed values from sensors of the radio tag sensor chips through the micro base stations, generates a spatial distribution map of the sensed values, and updates the spatial distribution map with time.

Systems and methods for sensor spatial distribution mapping using assigned sensor regions

A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmable wiring group. The reconfigurable circuit is also characterized in being provided with a fourth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the functional block input wiring group, and/or a fifth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the branch lines of the functional block output wiring.

Reconfigurable circuit

A reconfigurable device test scheme is provided for making a test of a reconfigurable device with configuration data which is loaded a smaller number of times. A reconfigurable device used herein holds a plurality of configuration data and is capable of instantaneously switching which configuration is implemented thereby. Specifically, one transfer configuration data and one or more test configuration data are previously loaded in a configuration memory of the reconfigurable device, and a test is made while sequentially switching the transfer configuration data and the test configuration data. In this way, the same configuration data need not be reloaded over and over, so that the test can be made with a smaller number of times of loading as compared with before.

Test system of reconfigurable device and its method and reconfigurable device for use therein

A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.

Reconfigurable circuit generation device, method, and program

A circuit design systemincludes storage meansto store structure description informationof a reconfigurable circuit including an array of cellsincluding a plurality of switches, and application circuit netlist informationused to specify an application, circuit generation unitto generate structure description informationbased on the structure description informationand the application circuit netlist informationstored in the storage means, and circuit evaluation unitto evaluate the structure description informationgenerated by the circuit generation unit, wherein the circuit generation unitgenerates the structure description informationby deleting at least one of the switchesfrom the structure description informationbased on an evaluation result obtained by the circuit evaluation unit

Circuit design system and circuit design method

Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks () having a full adder (), two preposition logics () that perform a plurality of logic operations according to configuration data, an extended logic block () that can perform the logic operation of one or more kinds. Outputs (A andB) of the preposition logic are respectively connected to two argument inputs (A and B) of the full adder (). A carry output (CO) of the full adder () is connected to the extended logic block (). One selected from a plurality of signals including a fixed logic value is input to a carry input (CI) of the full adder according to the configuration data, and the extended logic block of other logic block generates an output signal according to an output of the extended logic block.

Reconfigurable logical circuit

A plurality of three-terminal variable resistance switching elements each having a source electrode, a drain electrode, and a gate electrode are connected to each other in series. The source electrode of each of the three-terminal variable resistance switching elements and the drain electrode of its adjacent three-terminal variable resistance switching element are connected to each other through a wiring segment to form a lane. A potential holding section for holding a predetermined potential level is connected to the wiring segment. A column group is configured by selecting one of the three-terminal variable resistance elements in each lane. A common gate line is connected to each of the gate electrodes of the three-terminal variable resistance elements belonging to the column group.

Semiconductor device configuration method

A configurable circuit of the present invention includes a plurality of logic blocks (), and a programmable bus which can program connections of plurality of logic blocks (). The programmable bus includes a plurality of wires () arranged for each of signal transmission ranges corresponding to plurality of logic blocks (), direct wire connection switch () which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector () which can program a connection with any one of the plurality of wires, and programmable switch () which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches () are arranged for at least one of plurality of logic blocks ().

Configurable circuit and configuration method

A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Function block

A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and each vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel. In the horizontal programmable interconnect way, both the short horizontal programmable interconnect channel and the long horizontal programmable interconnect channel are constructed to have &ldquo;shift structure&rdquo;, thereby &ldquo;sector segmentation&rdquo; and problems related to the sector segmentation are avoided. The function cells are directly connected to the short horizontal programmable interconnect channel, but are not directly connected to the long horizontal programmable interconnect channel, therefore, signal transfer of input/output signals between the function cell and the long horizontal programmable interconnect channel is conducted necessarily through the short horizontal programmable interconnect channel and a programmable switch, thereby load capacitance on the long horizontal programmable interconnect channel is reduced and thereby high-speed signal transfer is realized.

Reconfigurable device having programmable interconnect network suitable for implementing data paths

A circuit for writing data to configuration memories is utilized to write initial value data to the configuration memories, thereby initializing the same. In addition, a transistor for providing disconnection between a writing data signal and an output signal of a configuration memory is inserted so that no collision occurs between both signals during the writing of data to the configuration memory.

Programmable function device and memory cell therefor

A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of &ldquo;1&rdquo;, and a fixed logic value of &ldquo;0&rdquo;. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit. A carry logic circuit has a ripple carry input terminal, a ripple carry output terminal, a ripple-core logic carry output terminal, a core logic carry generation input terminal, and a core logic carry propagation input terminal.

Growing community of inventors

Tokyo, Japan

Shogo Nakaya