International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Elpis Technologies Inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Shogo Mochizuki

Alexander Reznicek

Kangguo Cheng

Choonghyun Lee

Juntao Li

Oleg Gluschenkov

Veeraraghavan S Basker

Hemanth Jagannathan

Junli Wang

Chun-chen Yeh

Ruqiang Bao

Pouya Hashemi

Tenko Yamashita

Zuoguang Liu

Chun Wing Yeung

Hiroaki Niimi

Sanjay C Mehta

Nicolas J Loubet

Gen Tsutsui

Dechao Guo

Fee Li Lie

Ruilong Xie

Su Chen Fan

Huimei Zhou

Nicolas L Breil

Brent A Anderson

Joshua M Rubin

Peng Xu

Judson Robert Holt

Hong He

Ali Khakifirooz

Huiming Bu

Yunpeng Yin

Chiahsun Tseng

Jie Yang

Keith E Fogel

Zhenxing Bi

Chi-Chun Liu

Andreas Scholze

Chen Zhang

Xin Miao

Michael A Guillorn

Balasubramanian Pranatharthiharan

Soon-Cheon Seo

Heng Wu

Praneet Adusumilli

Dominic Joseph Schepis

Marc Adam Bergendahl

Koji Watanabe

Chun-Chen Yeh

Jody Alan Fronheiser

Timothy James McArdle

Yue Ke

Mona Abdulkhaleg Ebrish

Melissa Alyson Smith

ChoongHyun Lee

Eric C T Harley

Robin Hsin-Kuo Chao

Devendra K Sadana

Stephen W Bedell

Julien Frougier

Jingyun Zhang

Injo Ok

Joel Pereira De Souza

Michael P Belyansky

Raghavasimhan Sreenivasan

Pietro Montanini

Hao Tang

Mark V Raymond

Marinus Hopstaken

Jiseok Kim

Lawrence Alfred Clevenger

Ramachandra Divakaruni

Son Van Nguyen

Terence B Hook

Xiuyu Cai

Kisik Choi

Pranita Kerber

Qiqing Christine Ouyang

Yun-Yu Wang

Gauri V Karve

Richard Anthony Conti

Indira P Seshadri

Pierre Morin

Stuart A Sieg

Lan Yu

Dexin Kong

Albert M Young

Tao Li

Tsung-Sheng Kang

Kirsten Emilie Moselund

Derrick Liu

Yi Song

Ardasheir Rahman

Christopher Michael Prindle

Cezar Bogdan Zota

Toshiharu Nagumo

Tomohiro Hirai

A semiconductor structure includes a substrate disposed in a horizontal plane, a gate metal on the substrate, a first spacer and a second spacer on the substrate with the gate metal between the first spacer and the second spacer, and a plurality of horizontally stacked nanosheets extending between the first spacer and the second spacer, with the gate metal encapsulating the plurality of horizontally stacked nanosheets between the first spacer and the second spacer.

Horizontally stacked nanosheet gate all around device structure

A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Vertically stacked FET with strained channel

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Field effect transistor with backside source/drain

Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (stacked-FET). The stacked-FET includes a top FET having multiple top channels having multiple nano-sheets in contact with corresponding nano-sheets in a corresponding top channels for an active gate. The stacked-FET includes multiple bottom channels having a dielectric material. The semiconductor structure also includes an active gate. The active gate includes the corresponding top channels and corresponding bottom channels having the dielectric material.

Unipolar-FET implementation in stacked-FET CMOS

A semiconductor channel material structure is provided that has an improved, i.e., increased, effective channel area. The semiconductor channel material structure includes a plurality of semiconductor channel material nanosheets stacked one atop the other. The increased channel area is afforded by providing at least one through-stack semiconductor channel material that extends through at least one of the semiconductor channel material nanosheets.

Gate all-around device with through-stack nanosheet 2D channel

A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source/drain element of the first transistor to the first interconnect structure. The second contact connects a first source/drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

Stacked complementary transistor structure for three-dimensional integration

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

Embodiments of the invention are directed to a semiconductor-based structure that includes a stack having spaced-apart non-sacrificial nanosheets. A source or drain (S/D) trench is adjacent to the stack, wherein the S/D trench includes a bottom surface and sidewalls. A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.

Source or drain template for reducing strain loss in spaced-apart nanosheet channels

A semiconductor structure includes a p-type field-effect transistor region and an n-type field-effect transistor region. The p-type field-effect transistor region includes a strained channel of a composite of silicon germanium and silicon. The n-type field-effect transistor region includes a silicon channel.

Semiconductor device with strained channel

A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Isolation between vertically stacked nanosheet devices

A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Three-dimensional field effect device

A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.

Dual strained semiconductor substrate and patterning

A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices

A method includes forming a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and forming a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region. The second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers vertically stacked over the second region. An encapsulation layer is epitaxially grown along sidewalls of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers, and an oxide layer is formed in contact with a top surface of an uppermost second semiconductor channel layer of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers and in contact with opposite sidewalls of the encapsulation layer.

Sidewall epitaxy encapsulation for nanosheet I/O device

A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

Uniform interfacial layer on vertical fin sidewalls of vertical transport field-effect transistors

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Clifton Park, NY, United States of America

Shogo Mochizuki