Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Shogo Itai

Tadashi Kai

Tadaomi Daibou

Junichi Ito

Masahiko Nakayama

Hiroki Noguchi

Chikayoshi Kamata

Yasushi Nakasaki

Daisuke Saida

Masahiro Koike

Yuichi Ito

Toshiyuki Enda

Takamitsu Ishihara

Jyunichi Ozeki

Megumi Yakabe

Katsuyoshi Komatsu

Taichi Igarashi

According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Magnetic memory device including magnetoresistance effect element

According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.

Memory device

According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.

Magnetic device and memory device

According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.

Magnetic memory device and manufacturing method of the same

According to one embodiment, a magnetic memory device includes a first magnetic layer, a second magnetic layer, a third magnetic layer, and a first non-magnetic layer. The third magnetic layer is provided between a first part of the first magnetic layer and the second magnetic layer. The first non-magnetic layer is provided between the second magnetic layer and the third magnetic layer. The first magnetic layer further includes a second part. At least a portion of the second part overlaps at least a portion of the third magnetic layer in a second direction orthogonal to a first direction from the first part toward the second magnetic layer.

Magnetic memory device and nonvolatile memory apparatus

A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.

Nonvolatile memory with magnetoresistive element and transistor

Growing community of inventors

Kawasaki Kanagawa, Japan

Shogo Itai