Fujitsu Corporation

Shogo Fujimori

Masaki Tosaka

Makoto Suwada

Kazuhiko Tokuda

Yasuhiro Yamashita

Jiro Yoneda

Ryoji Yamada

Koutarou Nimura

Yoshiyuki Iwakura

Toshiro Sato

Tatsuo Koizumi

Kazumasa Kobayashi

Tendou Hirai

Daita Tsubamoto

Kazunari Gotou

Hitoshi Chida

Kazuyoshi Kanei

Toshirou Sato

A power supply noise analysis model creation method comprising; obtaining a distance which appears most frequently, from among the distances from a vias judged to be the nearest to the vias, respectively, as a reference via pitch, generates four nodes for the via of target wherein the four nodes generates the middle point with the other four via that are near the via of the target, obtaining meshes which include the nodes, respectively, by dividing the power island structure and the power supply pair by dividing lines which pass between the generated nodes, and converting each of the meshes obtained to a circuit element equivalent to the mesh.

Power supply noise analysis model creation method and apparatus, and recording medium storing program for power supply noise analysis model creation

A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.

Apparatus and method for eye margin calculating, and computer-readable recording medium recording program therefof

According to a circuit board creation program presented herein, a simulation assuming a case in which an addition of a bypass capacitor near a another bypass capacitor provided between a pin and via of an LSI part can be performed, simply by adding a bypass capacitor property model and changing the value of a coefficient parameter by which the property value of an element of a line part is to be multiplied or divided.

Technique for creating analysis model and technique for creating circuit board model

A design method includes creating power supply planes in each layer of a circuit board, from CAD data of the circuit boards whereby the power supply planes form one power supply conductor interconnect and supply power or connect to ground, expanding the shape of the power supply planes by a predetermined width, creating power supply pairs which are formed by opposing portions wherein two power supply planes existing in different layers are separated by an insulator and correcting the parameter by use of the mesh area.

Method, recording medium, and design support system for designing an electronics device

An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.

Power supply noise analysis model generating method and power supply noise analysis model generating apparatus

An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included in the electronic circuit, user requirements defined by a user, and user resources defined by the user, and urging an input to the user by displaying the design constraints.

Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method

The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus comprises an input information storage unitthat stores input information, an analytic model creation unitthat creates an analytic model of an electronic circuit on the basis of the input information, an analysis unitthat calculates an analysis result of the electronic circuit using the analytic model, a partial model reliability value databasethat defines the accuracy of each part of the analytic model and stores the accuracy value as a partial model reliability value, a partial model influence databasethat defines the magnitude of influence of each part of the analytic model and stores the influence value as a partial model influence, a reliability value evaluation unitthat calculates an analysis result reliability value, i.e. the reliability value of the analysis result, on the basis of the partial model reliability value and partial model influence, an analysis result determination unitthat determines whether the analysis result is good or bad, and a display unitthat displays the analysis result reliability value and the result of the good/bad determination.

Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program

Electronic circuit designing method and apparatus, and storage medium

A noise countermeasure determination method includes the step of obtaining an analyzing circuit judgement result by judging acceptability of the analyzing circuit based on a comparison of features of the analyzing circuit and transmission circuit topologies, and outputting an improvement proposal for making the analyzing circuit closer to one of basic types of the transmission circuit topologies depending on the analyzing circuit judgement result.

Noise countermeasure determination method and apparatus and storage medium

A noise countermeasure determination method includes the steps of calculating recommended circuit information considered to minimize a noise by use of at least one formula, based on input circuit information amounting to at least one net of a target circuit which is to be subjected to a noise analysis, and comparing the input circuit information and the recommended circuit information, and determining a differing portion of the recommended circuit information differing from the input circuit information, as noise countermeasures.

A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.

Growing community of inventors

Kawasaki, Japan

Shogo Fujimori