Dialog Semiconductor B.v.

Freescale Semiconductor,inc.

Shobak R Kythakyapuzha

Mahbub Reja

Gary A Kurtzman

Zhi Mou

Mohammad Hanif

Khurram Waheed

Ronald Clayton Alford

Jan Prummel

Jason H Branch

Chris N Stoll

David F Brown

Haolu Xie

Prachee S Behera

A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.

Divider circuit

A radio frequency input/output circuit with a composite inductor structure is presented. The composite inductor structure has a plurality of inductors that are interwound. The composite inductor structure is implemented on a chip. The plurality of inductors are magnetically coupled. The plurality of inductors are interwound around a core. A second inductor is coupled in series with a first inductor and the first inductor is coupled in series with the third inductor. The first inductor and the third inductor are coupled at a centre tap, such that the first inductor and the third inductor form a centre-tapped coil. The centre tap is coupled to an input terminal.

Radio frequency input/output for radio transceivers

A bias generator and a method for generating a bias voltage are presented. The bias generator is for use with an electronic circuit comprising a first switch coupled in series with a second switch. The bias generator is adapted to generate a reference voltage, a first bias voltage, and a second bias voltage. The second bias voltage is based on the reference voltage. After applying the first voltage to the first switch and the second voltage to the second switch, the bias generator controls a voltage across the first switch. The bias generator may be adapted to set a value of the reference voltage to control the voltage across the first switch. For instance, the reference voltage may be set to a fix value so that the voltage across the first switch is maintained at a constant value.

Bias generator

The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.

Switch-mode power amplifier for an RF transmitter employing digitally-controlled OOB harmonic attenuation techniques

A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

Systems and methods for operating radio transceivers

A PLL receives an indicator indicating that it is to operate at a different operating frequency than a current operating frequency. A control word is selected from a set of linear control words based upon the different operating frequency. A capacitance of a variable capacitor of a voltage-controlled oscillator is adjusted based upon the control word. The variable capacitor is monotonic and non-linear relative to the set of linear control words.

VCO control and methods therefor

An overtone crystal oscillator automatic calibration system including an overtone crystal oscillator with multiple programmable resistors and multiple amplifiers with supply voltage inputs and a calibration system. The calibration system adjusts the programmable resistors and the supply voltage inputs and detects oscillation of the overtone crystal oscillator. The calibration system adjusts the programmable resistors and the supply voltage input for each of multiple sequential steps to adjust the frequency bandwidth, such as from a higher bandwidth and lower gain to a lower bandwidth at higher gain. For example, each resistance level is tested for each of multiple supply voltage levels. The range of resistances and voltages is designed to ensure oscillation at a selected overtone frequency while avoiding oscillation at a fundamental frequency of the oscillator crystal. Oscillation may be detected by a counter which counts to a predetermined count value indicating successful oscillation.

Growing community of inventors

Round Rock, TX, United States of America

Shobak R Kythakyapuzha