Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer Hitachi, Ltd. & Engineering, Ltd.

Sho Yamamoto

Shuji Ikeda

Satoshi Meguro

Nobuyoshi Tanimura

Kotaro Nishimura

Osamu Minato

Makoto Saeki

Hideaki Nakamura

Masaaki Kubotera

Yasuo Yoshitomi

Kouichi Nagasawa

Kazuo Yoshizaki

Shingo Maeda

Yuki Koizumi

Isao Akima

Provided are a computer system and a program migration method capable of properly migrating programs between different computers. A first computer calculates a migration priority of each of the plurality of programs based on information which indicates weighting relative to usage of hardware resources, and operation information of hardware resources in the first computer when each of the plurality of programs is executed, and, based on hardware resource expansion schedule information which defines hardware resources of the second computer in each of a plurality of migration phases, determines migration feasibility of a program in hardware resources used in each migration phase and decides the migration phase for migrating each of the plurality of programs in order from a first migration phase of the plurality of migration phases and in order of the calculated migration priority.

Computer system and program migration method

An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Semiconductor memory device

A static RAM exhibiting a high reliability and suited to a higher density of integration is disclosed. In each memory cell of this static RAM, the cross coupling of a flip-flop circuit is made by gate electrodes of MISFETs constituting this flip-flop circuit. In addition, a source line is formed by the same step as that of a word line. A resistance value of a polycrystalline silicon layer which is a load resistor is changed in accordance with information to be stored. Furthermore, semiconductor regions for preventing soft errors attributed to alpha particles etc. are formed under the MISFETs constituting the flip-flop circuit, so that the channels are not adversely affected.

Semiconductor memory cell device with thick insulative layer

An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

MOS static type RAM having a variable load

An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Method for making static random-access memory device

An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

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Kodaira, Japan

Sho Yamamoto