United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Sho-Shen Lee

En-Chiuan Liou

Chien-Hao Chen

Chia-Hung Wang

Yi-Ting Chen

Hsiao-Lin Hsu

Yu-Cheng Tung

Chih-Wei Yang

Chang-Mao Wang

Wen-Liang Huang

Kai-Lin Chuang

Chien-Wei Huang

Jhao-Hao Lee

Yuan-Chi Pai

Chia-Ching Lin

Tuan-Yen Yu

Feng-Lun Wu

Chih-Yu Chiang

Chung-Ping Hsia

Yu-Chin Huang

Zheng-Feng Chen

Yi-Chih Chiang

Lu-Wei Kuo

The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Method for forming dynamic random access memory structure

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Manufacturing method for semiconductor pattern

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Method of forming layout of semiconductor device

A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

Method of forming overlay mark structure

The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Dynamic random access memory structure and method for forming the same

A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

Method for monitoring semiconductor process

The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.

Method for manufacturing semiconductor device

Measurement mark and method for monitoring semiconductor process

An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Overlay marks and semiconductor process using the overlay marks

A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.

Photomask and fabrication method thereof

A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.

Calculation method for generating layout pattern in photomask

A method of forming assist feature patterns includes providing an original layout pattern having at least a first region defined therein, the first region having a first light transmission rate larger than 0%; performing a search step to the original layout pattern to define at least a second region having a second light transmission rate equal to 0% in the original layout pattern; forming a plurality of assist features in the second region to increase the second light transmission rate to larger than 0%; and outputting the original layout pattern and the assist features to a reticle blank.

Growing community of inventors

Taipei, Taiwan

Sho-Shen Lee