Seiko Epson Corporation

Vweb Corporation

Other

Futuretel, Inc.

Intellectual Venture Funding LLC

Sho Long Chen

Le Trong Nguyen

Derek J Lentz

Sanjiv Garg

Stanley H Siu

Cheung Auyeung

Vivek Bhargava

Ren-Yuh Wang

Sanjiy Garg

Dengzhi Zhang

Richard H Tom

Gregory C Maturi

Gregory V Maturi

Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.

RISC microprocessor architecture implementing multiple typed register sets

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[]) and second (RA[]) subsets, and a shadow subset (RT[]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

A system and method is provided for variable bit rate encoding using a complexity ratio. Quantization parameter is calculated using a complexity ratio, which is equal to a local complexity divided by a global complexity. Complex pictures are allocated a larger bit budget relative to simple pictures. With the larger bit budget the quality of complex pictures can be maintained while reducing the overall size of the encoded video stream.

Video encoding using variable bit rates

A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a predetermined pattern of pixels in each macroblock rather than all the pixels of the macroblock. Reduction of computational overhead can be further enhanced first using a subpattern, i.e., a sub-sample of the predetermined pattern on a subset of the macroblocks to determine close matching macroblocks and then using the predetermined pattern to determine the best matching macroblock from within the close matching macroblocks.

Motion estimation using predetermined pixel patterns and subpatterns

A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a multi-phase computational scheme. Specifically, the pixel blocks the previous image are divided into different groups. The closest matching pixel block of each group is determined in a first phase. Then a more accurate difference measure is used to determine the origin block from among the closest matching pixel blocks.

Multi-phase motion estimation system and method

A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors by limiting the search for the origin block to a coarse search window and a fine search window within the coarse search window. The difference measure is computed for only a subset of pixel blocks within the coarse search window to reduce the computational overhead. However, to increase accuracy, the difference measure of all the pixel blocks in the fine search window are computed. The pixel block having the smallest difference measure is selected as the origin block.

Motion estimation using multiple search windows

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA&lsqb;23:0&rsqb;) and second (RA&lsqb;31:24&rsqb;) subsets, and a shadow subset (RT&lsqb;31:24&rsqb;). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

RISC microprocessor architecture implementing multiple typed register

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA�23:0!) and second (RA�31:24!) subsets, and a shadow subset (RT�31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

An apparatus and method for determining inter-frame motion during compression of digital video data incorporates a computationally efficient hierarchical block-matching motion estimation technique in conjunction with a full-search block-matching approach. In the hierarchical block-matching method, a macroblock is filtered and decimated, and a search area is also filtered and decimated. A block-matching search is performed within the filtered and decimated search area. An augmented block in the original search area that corresponds to the block in the decimated search area that provided the best match with the decimated macroblock is then compared with the original macroblock to determine a motion vector. Operating parameters specify the search range based on the type of frame being processed, i.e. P-frame or B-frame, and, in the case of B-frames, the distance of the B-frame from the reference frame. If the operating parameters specify a search range above an established threshold, the hierarchical block-matching search is performed. If the operating parameters specify a search range equal to or below the established threshold, the full-search block-matching search is performed.

Hybrid hierarchial/full-search MPEG encoder motion estimation

A coding conditions selection apparatus, adapted for inclusion in an MPEG-II encoder chip, and methods for selecting encoding parameters for a macroblock of video data includes an encoder decision block ('EDB') for receiving and concurrently stratifying into a plurality of blocks digital video data associated with a macroblock. Each block may correspond to video data for pels of the macroblock, or a block may correspond to differences produced by subtracting digital video data for pels of a reference frame of video from digital video data for pels of the macroblock. The EDB while evaluating functions, e.g. either a variance or a mean square error, concurrently processes the stratified data for several blocks while avoiding any redundant computations. A plurality of encoding conditions are determined based upon the block function evaluations.

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Saratoga, CA, United States of America

Sho Long Chen