Mitsubishi Electric Corporation

Nishikawa Co., Ltd.

Hitachi, Ltd.

Archem Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Hitachi Vantara Corporation

Sho Ikeda

Koji Tsutsumi

Hideaki Mogi

Yoji Shimura

Jun Yasukawa

Yasuyuki Nishikawa

Masaomi Tsuru

Mari Aoki

Kenichi Miyamoto

Mitsuhiro Shimozawa

Akihito Hirai

Osamu Kamimura

Hiroyuki Nagayama

Masataka Ogasawara

Akihiko Kawasaka

Akihiro Adachi

Kanna Matsuyama

Wataru Yamamoto

Shigeyasu Tsubaki

Hiroyuki Mizutani

Masahiko Usui

Takahiro Harada

Yosuke Ishida

Paritosh Vijay Kulkarni

Takafumi Enami

Kae Morita

A booster lever unit includes a first lever pivotably supported by an object via a first pivotal shaft, a second lever pivotably supported by the object via a second pivotal shaft, and a linkage member that links the first lever to the second lever. The pivotal plane of the first lever is parallel to the pivotal plane of the second lever. The first lever has one end provided with an operation section, and another end provided with the first pivotal shaft, and the first lever further includes a first linker, the first linker being provided between the operation section and the first pivotal shaft and linked to the linkage member. The second lever has one end provided with an action section, and another end provided with a second linker linked to the linkage member, and the second pivotal shaft is provided between the action section and the second linker.

Booster lever unit

Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.

Multi-resolution geometric representation using bounding volume hierarchy for ray tracing

Cushion

Cushion material

An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.

Electronic computing apparatus and enclosure therefor

A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal.

Phase-variable frequency multiplier and antenna device

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Phase synchronization device

A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.

Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

Phase synchronization circuit and in-phase distribution circuit

A lock detection circuit is configured to include an integrating circuit that integrates a phase difference between a frequency-divided signal of a VCO and a reference signal during a constant period within a transient response period for an output signal from the VCO, and integrates a phase difference between the frequency-divided signal and the reference signal during a constant period within a convergence period for the output signal from the VCO; and a degree-of-convergence calculating circuit that calculates a degree at which the output signal from the VCO has converged, from a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the transient response period and a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the convergence period.

Lock detection circuit and phase-locked loop circuit

A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit.

Phase-locked loop circuit

A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

PLL circuit

Growing community of inventors

Tokyo, Japan

Sho Ikeda