Cadence Design Systems, Inc.

Corekt Security Systems, Inc.

Shmuel Sagiv

Andreas Kuehlmann

Kenneth L McMillan

Yona Hollander

Ophir Rahman

Ury Segal

In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.

General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software

Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software

Method for detecting buffer overflow weakness exploitation, including the steps of determining a plurality of threshold parameters, each respective to a buffer overflow weakness exploitation event, analyzing a code to be executed, thereby producing a plurality of validation values, comparing said validation values to the respective ones of the threshold parameters, and determining a buffer overflow weakness exploitation attempt, when at least one of the validation values exceeds the respective one of the threshold parameters.

Method for detecting buffer overflow for computer security

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Tel Aviv, Israel

Shmuel Sagiv