Other

Monolithic Memories, Inc.

Shlomo Waser

John M Birkner

Ury Priel

William E Moss

Hua T Chua

Robert C Ghest

A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port. Multiplexing means and register means interact with the control circuits to formulate the data transfers.

Bidirectional dual port serially controlled programmable read-only memory

A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products. A carry/save arithmetic logic unit operates in conjunction with the registers to cause accumulation and storage of multiplication products and division quotient/remainders in the double length accumulator registers which provide a 32 bit output number. BACKGROUND OF THE INVENTION

High-speed digital bus-organized multiplier/divider system

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Sunnyvale, CA, United States of America

Shlomo Waser