Intel Corporation

Microsoft Technology Licensing, LLC

Shlomo Raikin

Gad Shlomo Sheaffer

Ehud Cohen

Zeev Sperber

Stanislav Shwartsman

Raanan Sade

Robert Valentine

Igor Yanover

Vadim Bassin

Shay Gueron

Julius Yuli Mandelblat

Oleg Margulis

Hisham Shafi

Gur Hildesheim

Gal Ofir

Guy Patkin

Ittai Anati

Gideon Gerzon

Geeyarpuram N Santhanakrishnan

Mohan J Kumar

Uday R Savagaonkar

Carlos V Rozas

Francis X Mckeen

David J Sager

Ron Gabor

Joseph Nuzman

Michael Mishaeli

Michael A Goldsmith

Ganapati Srinivasa

Theodros Yigzaw

Jose Andy Vargas

Ho-Seop Kim

Ron Shalev

Prashant Dewan

Youfeng Wu

Koichi Yamada

Robert S Chappell

Zvika Greenfield

Larisa Novakovsky

Tin-Fook Ngai

Ruchira Sasanka

Suresh Srinivas

Jayaram Bobba

Omar M Shaikh

Leeor Peled

Howard Chen

Jason A Domer

Joydeep Ray

Ali-Reza Adl-Tabatabai

Geoffrey S Strongin

Blaise B Fanning

Jan Stephen Gray

Ilan Pardo

Niranjan L Cooray

Lihu Rappoport

Adi Yoaz

David S Callahan

Ofer Levy

Zeev Offen

Jeffrey J Cook

Rohit Bhatia

Doron Orenstien

David W Burns

Sebastien Hily

Alex Berenzon

Ariel Berkovits

Eran Shifer

Yiftach Gilad

Iris Sorani

Evgeni Krimer

Michael D Tucknott

Prakash Math

Pankaj Raghuvanshi

Evgeny Bolotin

Michael S Bair

Melih Ozgul

Dewan Prashant

Ori Lempel

Jeffery J Cook

Levy Ofer

Adi Basel

Omer Golz

Leslie A Ong

Michelle J Moravan

Doron Orenstlen

Dannie G Feekes

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Scatter using index array and finite state machine

Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

Gather using index array and finite state machine

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

Apparatus and method for memory-hierarchy aware producer-consumer instruction

Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

Virtual memory address range register

A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.

Registering a user-handler in hardware for transactional memory event handling

Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Hybrid exclusive multi-level memory architecture with memory management

A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

Access type protection of memory reserved for use by processor logic

Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

Obscuring memory access patterns in conjunction with deadlock detection or avoidance

Growing community of inventors

Geva Carmel, Israel

Shlomo Raikin