Oki Electric Industry Co., Ltd.

Shizuo Cho

Masaru Uesugi

Norihiko Satani

Tsuneo Takano

Yuichi Matsushita

Junichi Suyama

Tetsuya Mitoma

A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting an output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor between the first and second electrodes for inputting the first node obtained based on the output data signal, and outputting the output node.

Level adjustment circuit and data output circuit thereof

A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting an output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor between the first and second electrodes for imputing the first node obtained based on the output data signal, and outputting the output node.

A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundant memory cells each of which is coupled to one of the word lines and to the redundant bit line. The device further includes a coincidence circuit that receives a first address signal, indicating an address of one of the normal bit lines, and a second address signal, indicating an address of one of the normal bit lines to which a defective memory cell is coupled, and which selects the redundant bit line when the first address signal coincides with the second address signal. A logic circuit included in the device also receives the first address signal and the second address signal and selects one of the normal bit lines according to the first address signal, but is inhibited from selecting the normal bit line coupled to the defective memory cell identified by the second address signal.

Semiconductor memory device having redundant circuit

A bias circuit supplies a predetermined current to a next-stage circuit. The bias circuit comprises a first node having a first potential, a second node having a second potential, an output node electrically connected to the next-stage circuit, a main bias circuit electrically connected to the first node and the output node and for supplying the predetermined current from the first node to the output node, and an auxiliary bias circuit electrically connected to the first and second nodes and the output node and for equalizing the value of a current flowing from the first node to the output node to the value of a current flowing from the output node to the second node.

Bias circuit for providing a stable output current

An output buffer circuit comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal. The bootstrap circuit comprises a delay circuit for delaying the input signal to provide a delayed input signal, a first transistor for receiving a signal inverted from the input signal, a second transistor coupled for receiving the delayed input signal and controlling a the first transistor, a third transistor connected in parallel to the second transistor, a fourth transistor coupled a gate of the third transistor for receiving the input signal and a charge circuit coupled between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appeared on the first node and the delayed input signal.

Bootstrapped high-speed output buffer

A semiconductor memory device according to the present invention comprises a first and second nodes, a first power supply for supplying a supply power potential to the first node, a memory cell for storing data therein; a bit line connected to the memory cell, a sense amplifier connected to the second node, for amplifying a potential of the bit line; a switching circuit connected between the first and second nodes, for coupling the first node with second node in response to a first control signal and substantial disconnecting the first node from the second node in response to a second control signal, a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantialy equal to the supply power potential, a control circuit applied an address signal having a first or second logic level thereto, for outputting the first control signal in response to the address signal being the first logic level and outputting the second control signal in response to the detection signal after the address signal being the second logic level.

Semiconductor memory device

To avoid unnecessary power dissipation, a decoder for selecting redundant memory cells in a memory device provides, for each section of the memory device, a first node and a second node that are coupled through a fuse-programmable ROM. If a defective memory cell is found in a section of the memory device, the fuse-programmable ROM of that section is programmed so as to decouple the first node from the second node when the defective memory cell is addressed. Prior to every access cycle, the first and second nodes of all sections are precharged. When address signals are received, the second node of the addressed section is discharged, other second nodes remaining charged. Normal or redundant memory cells are selected by performing a logic operation on the potentials of the first nodes.

Low-power decoder for selecting redundant memory cells

A dynamic random access memory comprising a matrix of memory cells accessed via word lines and bit lines also has clamp signal lines. The word lines terminate at switching elements, controlled by the clamp signal lines, through which the word lines are normally clamped to ground. In a memory access or refresh cycle, the selected word line is temporarily disconnected from ground by activating the corresponding clamp signal line. At the end of the cycle, the selected word line is again clamped to ground prior to precharging of the bit lines, in preparation for the next cycle. Non-selected word lines remain clamped to ground at all times, which prevents noise and improves data retention. Unnecessary current dissipation is avoided because switching elements are switched and word lines are unclamped only when necessary.

Random access memory including word line clamping circuits

An integrated circuit memory device includes a sense amplifier circuit having a first transistor coupling section connected between a pair of bit lines and a pair of sense amplifier nodes. The first transistor coupling section selectively connects the bit lines and the sense amplifier nodes in response to a first control signal. The sense amplifier circuit further includes a first sense amplifier connected between the sense amplifier nodes so as to selectively discharge one of the sense amplifier nodes and a second sense amplifier connected between the sense amplifier nodes so as to selectively charge the other one of the sense amplifier nodes. The first control signal can have a first voltage substantially intermediate a potential equal to a potential threshold of a transistor in the first transistor coupling section and the sum of a potential equal to the potential threshold and a precharge potential at the beginning of a sense operation. At these voltage levels, the first transistor is operative to decouple a first sense node from a first bit line when a selected memory cell stores a logic ONE level while a second transistor connects a second sense node with as second bit line. Also, the second transistor is operative to decouple the second sense node from the second bit line when the selected memory cell stores a logic ZERO level while the first transistor connects the first sense node with the first bit line.

Sense amplifier circuitry selectively separable from bit lines for

A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit lines pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be stored. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dumy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.

Semiconductor memory circuit having dummy cells connected to twisted bit

A reference voltage generating circuit in a CMOS semiconductor integrated circuit comprises a first reference voltage circuit for generating a first reference voltage by means of a MOS transistor having a first channel type, a second reference voltage circuit for generating a second reference voltage by means of a MOS transistor having a second channel type, and a comparator circuit for comparing the first and second reference voltages and feeding back the output corresponding to the result of the comparison, to the first reference voltage circuit to produce a third reference voltage.

Reference voltage generating circuit

A semiconductor memory such as a dynamic RAM (Random Access Memory) implemented by complementary MOS (CMOS) transistors includes a plurality of bit line pairs each constituted by a first and a second complementary bit line for transferring data, and a plurality of word lines extending across the bit line pairs. A plurality of memory cells are located at the intersecting points of the bit line pairs and word lines and connected to the latter for storing data therein. A plurality of sense amplifier circuits are each associated with respect to one of the bit line pairs for sensing potentials on a first and a second node associated with the bit line pair and amplifying the sensed potentials. Each of the sense amplifier circuits includes a first and a second sense amplifier of opposite polarity. A plurality of first field effect transistors (FETs) each has a source-drain path for connecting to the first node the first bit line of respective one of the bit line pairs. A plurality of second FETs each has a source-drain path for connecting to the second node the second bit line of respective one of the bit line pairs. The plurality of first and second field effect transistors individually have commonly connected control electrodes to which a gate signal is applied. The plurality of first and second field effect transistors are complementarily controlled in response to the gate signal to transfer one of the potentials on the first and second bit lines to one of the first and second sense amplifiers.

CMOS RAM having a complementary channel sense amplifier

A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.

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Miyazaki, Japan

Shizuo Cho