Hong Kong Applied Science and Technology Research Institute Company, Limited

Shiyuan Zheng

Tat Fu Chan

Yunlong Li

Wang Chi Cheng

Chi Fung Lok

Zhiwei Wu

A Phase-Locked Loop (PLL) has a multi-curve voltage-controlled oscillator (VCO) with a curve-select input that adjusts the capacitance within the VCO and thus the VCO gain. A calibration unit generates a curve-select value to the VCO. Coarse calibration selects a Center Curve CC value using binary search of the curve-select bits. During fine calibration, the number of pulses of the VCO output are counted and stored for all curves in a target window around the center curve. The stored pulse counts are compared to an ideal pulse count for a specified frequency, and the curve-select value for the closest-matching pulse count is applied to the VCO. The target window is much smaller than all possible curves, so calibration is performed only on a few curves, reducing calibration time. A switch before the VCO opens the loop for faster open-loop calibration. Pulses are counted digitally without expensive analog comparators.

Fast coarse tune and fine tune calibration for a synthesizer by multi-curve calibration within a target window

A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

Gain calibration for direct modulation synthesizer using a look-up table searched by a reduced count from an overflow counter

Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.

Harmonics suppression circuit for a switch-mode power amplifier

A multi-stage Successive-Approximation Register (SAR) pipeline Analog-to-Digital Converter (ADC) has an amplifier between two switched capacitor networks, each controlled by a SAR. The load capacitance of the amplifier is magnified due to the amplifier's gain. This magnified load capacitance can disproportionately increase power consumption. The back plates of the second-stage switched capacitors are connected to the amplifier input using a feedback switch during an amplification phase, so that the second-stage switched capacitors are connected between the input and output of the amplifier as a feedback capacitor, rather than a load capacitor. Reset switches are added to drive both plates of the second-stage switched capacitors to ground during a reset phase before the amplification phase. Thus the second-stage switched capacitors function as both the feedback capacitor and as the switched capacitors controlled by the second SAR. Amplifier power is reduced since there is no separate load capacitor during the amplification phase.

Loading-free multi-stage SAR-assisted pipeline ADC that eliminates amplifier load by re-using second-stage switched capacitors as amplifier feedback capacitor

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Hong Kong, China

Shiyuan Zheng