Xilinx, Inc.

Shiyao Ge

Saikat Bandyopadhyay

Rajvinder S Klair

Tapodyuti Mandal

Dhiraj Kumar Prasad

Ashish Kumar Jain

Miti Joshi

Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

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San Jose, CA, United States of America

Shiyao Ge