The 13Th Research Institute of China Electronics Technology Group Corporation

The 13Th Research Institute of China Electronics

Shixiong Liang

Zhihong Feng

Yuangang Wang

Yuanjie Lv

Xubo Song

Xin Tan

Xingye Zhou

Zezhao He

Chuangjie Zhou

Cui Yu

Xingchang Fu

Shaobo Dun

Hongyu Guo

Xuefeng Zou

Dong Xing

Peng Xu

Junlong Wang

Dabao Yang

Lisen Zhang

Xiangyang Zhao

A ultraviolet detector includes a substrate; a first epitaxial layer that is a heavily doped epitaxial layer and located on the substrate, a second epitaxial layer located on the first epitaxial layer, where the second epitaxial layer is a lightly doped epitaxial layer, or a double-layer or multi-layer structure composed of at least one lightly doped epitaxial layer and at least one heavily doped epitaxial layer; an ohmic contact layer located on the second epitaxial layer or formed in the second epitaxial layer, where the ohmic contact layer is a graphical heavily doped layer; and a first metal electrode layer located on the ohmic contact layer.

Ultraviolet detector and preparation method therefor

The disclosure provides a preparation method of GaN field effect transistor based on diamond substrate, and relates to the technical field of semiconductor manufacturing. The method includes the following steps: preparing a GaN heterojunction layer on the front-side of a SiC substrate; thinning the SiC substrate; etching the SiC substrate; growing a diamond layer; removing a sacrificial layer and the diamond layer on the sacrificial layer; preparing a source electrode, a drain electrode and a gate electrode on the front surface of the GaN heterojunction layer; etching the SiC substrate and the GaN heterojunction layer to form a source through hole communicated with the source electrode; and removing the through hole mask layer, and preparing back grounding metal to complete the preparation of the diamond substrate GaN transistor device.

Preparation method of GaN field effect transistor based on diamond substrate

The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.

Normally-off gallium oxide field-effect transistor structure and preparation method therefor

The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an Nhigh-concentration substrate layer, an Nlow-concentration GaOepitaxial layer and an anode metal layer from bottom to top, wherein the Nlow-concentration GaOepitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Gallium oxide SBD terminal structure and preparation method

The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Method for preparing isolation area of gallium oxide device

The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Method for preparing self-aligned surface channel field effect transistor and power device

An unbalanced terahertz frequency doubler circuit with power handling capacity is provided, and the circuit includes a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Unbalanced terahertz frequency doubler circuit with power handling capacity

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Shijiazhuang, China

Shixiong Liang