Sk Hynix Nand Product Solutions Corp.

Intel Corporation

Shivashekar Muralishankar

Shankar Natarajan

Yihua Zhang

Arun Athreya

Bartosz Kot

Mariusz Dolny

Suresh Nagarajan

Sriram Natarajan

Michal Mamczyński

Michał Mamczyński

A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.

Methods and systems for software based prefetching for low buffer depth sequential read traffic

An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

Dynamic single level cell memory controller

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Folsom, CA, United States of America

Shivashekar Muralishankar