Micron Technology Incorporated

Shivani Srivastava

Sanh D Tang

Fatma Arzum Simsek-Ege

Marsela Pontoh

Song Guo

Lavanya Sriram

Vlad Temchenko

Sharmila Velamur

Kunal Shrotri

Fawad Ahmed

Byung Yoon Kim

Yong Mo Yang

Hyuck Soo Yang

Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

Apparatuses including Finfets having different gate oxide configurations, and related computing systems

Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

Edge device

A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30&#xb0; to about 75&#xb0; relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0&#xb0; to about 90&#xb0; relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related memory devices and electronic systems

Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices

Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000&#xb0; C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050&#xb0; C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000&#xb0; C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050&#xb0; C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

DRAM cells and methods of forming silicon dioxide

Growing community of inventors

Boise, ID, United States of America

Shivani Srivastava