National Semiconductor Corporation

Eastman-kodak Company

Shivani Gupta

Christina P Phan

Bumha Lee

Willem J Kindt

A circuit and method for increasing the dynamic range of CMOS image sensors designed with a thin gate oxide layer. The circuit includes a high voltage supply circuit and a high voltage level shifter circuit. The high voltage supply circuit is configured to supply a voltage to the shifter circuit. The voltage has a voltage level higher than the maximum supply voltage of the associated fabrication process. The shifter circuit is configured to output a high reset signal based on a reset signal generated to reset a pixel circuit of a pixel array. Instead of the reset signal, the high reset signal is coupled to a gate of the reset transistor in the pixel circuit. The high reset signal allows the reset transistor to maintain a gate to source potential less than the maximum supply voltage even when the high reset signal is greater than the maximum supply voltage.

High voltage reset method for increasing the dynamic range of a CMOS image sensor

A charge-pump circuit generates a constant voltage higher than the available power supply. A feedback path maintains the voltage at a constant level in spite of power supply, temperature and process variations. This charge pump circuit includes a switched capacitor interface arranged to generate a target voltage that is used to activate and deactivate a bypass capacitor interface to maintain the constant voltage. The bypass capacitor interface is configured to complete the feedback path. The feedback helps to ensure that node n1, that is coupled to the output of the charge pump, stays at a constant potential, irrespective of the power supply voltage.

Constant voltage charge-pump circuit with feedback

An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e.g., load capacitance due to parasitic capacitance) at at least one sensitive node, including the steps of identifying a sensitive node of a preliminary design for the circuit, wherein an array of switches is coupled to the sensitive node; and determining a refined design for the circuit in which the array is replaced by a segmented switch array comprising switches connected between nodes having a tree structure, wherein the nodes include a root node, and the root node is the sensitive node.

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Milpitas, CA, United States of America

Shivani Gupta