Synopsys, Inc.

Shivangi Mittal

Prashant Dubey

Jamil Kawa

Ishita Satishchandra Desai

Surya Prakash Gupta

Raushan Kumar Jha

An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.

Read-write architecture for low voltage SRAMs

A data storage element comprises a master stage (MS) with a first and a second latch (LI, L), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT) based on an input signal (DATA) in relation to a first threshold level (TP). The second latch generates (L) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT) based on the input signal (DATA) in relation to a second threshold level (TP). The second threshold level (TP) is distinct from the first threshold level (TP). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT, DOUT) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT, DOUT) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.

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Delhi, India

Shivangi Mittal