Advanced Micro Devices Corporation

Shivananda S Shetty

Jeffrey P Erhardt

Paul J Steffan

Srikanth Sundararajan

Siu May Ho

Franklyn Shihyu Wu

John JianShi Wang

Mehrdad Mahanpour

David C Newbury

Jerry H G Tsiang

W Eugen Hill

A tester information tester information processing system provides test equipment for generating test data. A markup language encoder connected to the test equipment encodes the test data for storage in an object-oriented database management system connected to the markup language encoder, and a user interface is operatively connected to the object-oriented database management system for retrieval of the test data.

Method and system for storing and retrieving semiconductor tester information

A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.

Efficient storage of fail data to aid in fault isolation

A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.

Method and apparatus for correlating semiconductor process data with known prior process data

A method for analyzing a semiconductor device tests a semiconductor device to produce first and second data. A clustering method is applied to the first data, creating a clustered first data. The clustered first data is then correlated with the second data to determine analyzed data.

Method and apparatus for using clustering method to analyze semiconductor devices

A system and method for processing tester information is provided having a system-under-test. A pattern is written to the system-under-test, and a pattern is read therefrom. The pattern written is then compared to the pattern read from the system-under-test. The signal from the comparison is processed, and the signal from the signal processing is then analyzed.

Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development

A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.

Wafer level global bitmap characterization in integrated circuit technology development

A method and system of processing tester information of a system under test is provided. Data of a tested characteristic of the system under test is generated. A distribution curve is extracted from the data. A signature of the distribution curve is determined, and a map of the signature on a depiction of the system under test is presented. The distribution curve also can be categorized in a plurality of bins, and bitmaps are generated for the sections in each of the plurality of bins. Systematic signatures are determined from the bitmaps in the block, and the signatures are correlated with the locations on the system under test.

Characterizing distribution signatures in integrated circuit technology

A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

Method and system for using emission microscopy in physical verification of memory device architecture

A system and method are provided for processing tester information including means of determining axis information and means of determining break information for the tester information. The axis information and the break information are applied to the tester information to provide disjointed tester information. The disjointed tester information is then plotted on a disjointed axis graph.

System and method for processing tester information and visualization for parameter with multiple distributions in integrated circuit technology development

A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.

Testing multiple levels in integrated circuit technology development

A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.

Determination of nonphotolithographic wafer process-splits in integrated circuit technology development

A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.

Method of simultaneous display of die and wafer characterization in integrated circuit technology development

A method for processing tester information is provided. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts.

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Sunnyvale, CA, United States of America

Shivananda S Shetty