Cadence Design Systems, Inc.

Clk Design Automation, Inc.

Shiva Raja

Igor Keller

Ling Wang

Joao Moreno Geada

Lizheng Zhang

Isadore T Katz

James Kuzeja

Leon LaFrance

Venkat Thanvantri

Ferenc Varadi

Ahran Dunsmoor

The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.

Characterizing electronic component parameters including on-chip variations and moments

A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.

Database based timing variation analysis

Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.

Method and system for crosstalk analysis

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Chelmsford, MA, United States of America

Shiva Raja