Stmicroelectronics International N.v.

Shiv Kumar Vats

Venkata Narayanan Srinivasan

Umesh Chandra Srivastava

Manish Sharma

Tripti Gupta

Himanshu

V Narayanan Srinivasan

According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

Area, cost, and time-effective scan coverage improvement

In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Scan circuit and method

An integrated circuit includes a first set and a second set of scan flip flops, a circuit under test, and a controller. Each scan flip flop of the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip flop downstream of the logic elements. Each scan flip flop of the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic elements by shifting test patterns into the first set while asserting both the first and second scan enable signal, launching the test patterns, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

Test pattern generation using multiple scan enables

In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

Circuit and method for scan testing

A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.

Growing community of inventors

Greater Noida, India

Shiv Kumar Vats