Intel Corporation

Shiv Kaushik

Dion Rodgers

Hong Wang

Baiju V Patel

Gautham N Chinya

John Thomas Shen

Bryant E Bigbee

Richard A Hankins

James Paul Held

Hong Jiang

Gad Shlomo Sheaffer

Per H Hammarlund

Yuval Yosef

Yoav Talgam

James B Crossland

David A Koufaty

Deborah T Marr

Anil Aggarwal

David Lawrence Hill

Prashant Sethi

Russell Jerome Fenger

Xiang Chris Zou

Trung Am Diep

John L Reid

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior.

System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms

Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible 'shreds' of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Mechanism to emulate user-level multithreading on an OS-sequestered sequencer

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Growing community of inventors

Portland, OR, United States of America

Shiv Kaushik