Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Shiv Harit Mathur

Nitin Kumar Gupta

Ramakrishnan Subramanian

Anand Sharma

Vinayak Ashok Ghatawade

Ashish Savadia

Rajeswara Rao Bandaru

Yan Li

Venkatesh Ramachandra

Dmitry Vaysman

Elkana Richter

Sateesh Desireddi

Vijay Chinchole

Jayanth Mysore Thimmaiah

Srinivasa Rao Sabbineni

Lakhdar Iguelmamene

Rampraveen Somasundaram

Richard J K Hong

Tejaswini K

Siva Raghu Ram Voleti

Avinash Pandit

Sai Ravi Teja Konakalla

Nirav Natwarbhai Patel

Niravkumar Natwarbhai Patel

Siddesh Darne

An apparatus is provided that includes a first pull-up driver circuit coupled to a first calibration node, an internal resistor circuit and first input/output pad on an integrated circuit die, a second pull-up driver circuit coupled to a second calibration node and second input/output pad on the integrated circuit die, a third pull-up driver circuit coupled to a third calibration node, a comparator including a first input terminal selectively coupled to the first calibration node, the second calibration node and the third calibration node, and a second input terminal coupled to a reference voltage, and circuitry configured to trim the reference voltage to compensate for a comparator offset, and trim an impedance of the internal resistor circuit by comparing a voltage on the first calibration node and the trimmed reference voltage. The trimmed impedance of the internal resistor circuit substantially equals a desired impedance of the third pull-up driver circuit.

Dual reference ZQ calibration circuits and methods

Embodiments of the disclosed technology relate to the operation of devices including memory devices, and more particularly to valid window maximization in a toggle mode (TM) or Open NAND Flash Interface (ONFI) link using systematic skew while compensating for simultaneous switching outputs (SSO) and cross talk.

System and method for valid window maximization in toggle mode link using systematic skew addition to compensate for SSO and crosstalk

Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be enabled when the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance. The voltage mode driver may also be a pullup design, or have both pulldown and pullup stages.

PPA improvement for voltage mode driver and on-die termination (ODT)

An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

High speed toggle mode transmitter with capacitive boosting

Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.

Two-stage high speed level shifter

Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.

Reference independent and noise insensitive glitch free clock multiplexer

Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.

Snapback electrostatic discharge protection for electronic circuits

Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.

Dual voltage high speed receiver with toggle mode

The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a buffer circuit that increases the slew rate of a signal that controls a discharge circuit. In some aspects, the ESD protection includes a voltage-dependent resistance circuit that adjusts a time constant of a resistive-capacitive filter based on a voltage on a supply node.

Electrostatic discharge protection circuit

A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.

High-level output voltage training for non-volatile memory

A data storage system includes a memory including a plurality of memory cells; and an interface coupled to the memory and a host. The interface includes a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal. The interface further includes a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to apply an impedance or forego applying an impedance to the multi-level data signal based on a previous state and a current state of the multi-level data signal.

Multi-level signaling scheme for memory interface

A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D-D, to either be non-inverted or inverted, to save power consumed in the memory device.

Transmitting DBI over strobe in nonvolatile memory

An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

System and method for a reconfigurable controller bridge chip

A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.

Growing community of inventors

Bengaluru, India

Shiv Harit Mathur