Fujitsu Corporation

Shiuji Sakakura

Yukio Suda

Yasuhiro Ooba

Isao Chiku

Masayuki Horie

A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.

Cross-connect system and cross-connect method

In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.

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Kawasaki, Japan

Shiuji Sakakura