Taiwan Semiconductor Manufacturing Comp. Ltd.

Shiu-Ko JangJian

Chi-Cherng Jeng

Ting-Chun Wang

Chih-Nan Wu

Chun-Che Lin

Volume Chien

Chun Che Lin

Cheng-Ta Wu

Ying-Lang Wang

Min Hao Hong

Kei-Wei Chen

Yun-Wei Cheng

Chia-Yang Wu

Chi-Wen Liu

Szu-An Wu

Jia-Ming Lin

Chung-Ren Sun

Wei-Barn Chen

Ting-Huang Kuo

Chi-Cheng Hung

Jun-Nan Nian

Yung-Si Yu

Tzu-Kai Lin

Yu-Sheng Wang

Chih-Mu Huang

Wei-Ken Lin

Kuo-Cheng Lee

Chih-Tsung Lee

Yu-Ku Lin

Chung-Wen Wu

Chien-Chung Chen

Miao-Cheng Liao

Cheng-Wei Chen

Tsung-Hsuan Hong

Chien-Wen Chiu

You-Hua Chou

Zhe-Ju Liu

I-i Cheng

Chin-Nan Wu

Kuang-Yao Lo

Wen-Cheng Hsuku

Horng-Huei Tseng

Hsin-Chi Chen

Chii-Ming M Wu

Chen-Ming Huang

Wei-Ming You

Fu-Tsun Tsai

Yu-Ren Peng

Yu-Jen Chien

Chuan-Pu Liu

Kun-Ei Chen

Keng-Chuan Chang

Chen-Cheng Chou

Kun-Tzu Lin

Ren-Hau Yu

Ting-Siang Su

Phil Sun

Shih-Chieh Chang

Ming-Te Chen

Hung-Hsu Chen

Sheng-Wen Chen

Chiu-Jung Chen

Hsiang Hsiang Ko

Ing-Ju Lee

Chih-Cherng Jeng

Che-Min Lin

Hong-Yi Wu

Jyun-Ru Wu

Hsiang-Hsiang Ko

Chen-Chun Chen

Chun Hsiung Tsai

Ziwei Fang

Chun-Chieh Wang

Yu-Ting Lin

Yung-Lung Hsu

Ching-Hwanq Su

Huai-Tei Yang

Yu-Jen Chen

Tsung-Han Tsai

Chyi-Tsong Ni

Shih-Chi Lin

Chih-Ming Lee

Fu-Cheng Chang

Yao-Hsiang Liang

Chung-En Kao

Hung Jui Chang

Chen-Chieh Chiang

Ping-Pang Hsieh

Wen-Long Lee

Wei Chih Lin

Ming-Chin Tsai

Yi-Hsing Chu

Chia-Hung Chung

Guang-Cheng Wang

Ying-Min Chou

Jinn-Kwei Liang

Min-Hao Hong

Tzu Kai Lin

Jun Wu

Huan-En Lin

A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.

Semiconductor device

Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

Flat STI surface for gate oxide uniformity in Fin FET devices

An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Interconnection structure and manufacturing method thereof

An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.

Image sensor device

A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

Method for manufacturing semiconductor structure

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

Structure and formation method of fin-like field effect transistor

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the contact layer passes through the first barrier layer, the first barrier layer passes through the second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of a sidewall of the first barrier layer and exposes a first lower portion of the sidewall of the first barrier layer, and the sidewall faces away from the contact layer.

Semiconductor device structure with barrier layer

A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.

Semiconductor device having planar transistor and FinFET

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first, second, third and fourth fin structures over a substrate. The first and the second fin structures have a first and a second sidewall surfaces respectively. The third and the fourth fin structure have a third and a fourth sidewall surfaces respectively. The first and the second sidewall surfaces extend along a first direction. The third and the fourth sidewall surfaces extend along a second direction different from the first direction. A first and a second isolation structures are over the substrate and surrounding the first and the second fin structure and surrounding the third and the fourth fin structures respectively. A distance between top portions of the third and the fourth sidewall surfaces is greater than that between top portions of the first and the second sidewall surfaces.

Fin field effect transistor (FinFet) device structure and method for forming the same

An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Etch stop layer in integrated circuits

A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Conductive contact having barrier layers with different depths

A semiconductor device structure is provided. The semiconductor device structure includes a contact layer over a metal silicide layer. The contact layer extends through a first dielectric structure. The semiconductor device structure includes a first metal nitride barrier layer over sidewalls of the contact layer. The first metal nitride barrier layer is directly adjacent to the first dielectric structure. The semiconductor device structure includes a second metal nitride barrier layer partially between the contact layer and the metal silicide layer and partially between the contact layer and the first metal nitride barrier layer. The metal silicide layer is below the first metal nitride barrier layer and the second metal nitride barrier layer.

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Electrochemical plating system and method of using

A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S&#x2014;H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.

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Tainan, Taiwan

Shiu-Ko JangJian