Industrial Technology Research Institute

Shisheng Shang

Chia-Chang Hsu

Chung-Chih Chang

Shyh An Chi

Tzi Ting Huang

In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the microinstructions translated from a macroinstruction using two control bit data, accelerate the reaction time to interrupts, and expand the time frame within which to process interrupts while maintaining a precise interrupt. When a macroinstruction is decoded into microinstructions at the decoder stage in a pipelined data processor, a control bit called the atomic bit provides the system with the information about the boundary of the precise interrupt, and another control bit called the LOCK bit decides when an external interrupt can be processed and masks an interrupt when the system state does not allow any interrupt to be processed.

Apparatus and method for generating an interrupt prohibited zone in pipelined data processors

In a fast response time pipelined data processor, an interrupt control device stores the interrupt service routine address or the target address of a branch instruction, as applicable, in a register. If an interrupt occurs while the pipelined data processor is processing a branch instruction, the branch instruction target address stored in the register is used as the return address, and is stored in a working space, so that the interrupt can be processed immediately. Similarly, if an interrupt occurs while the pipelined data processor is processing a prior interrupt or exception, and the first instruction of the interrupt service routine of the previous interrupt has not yet reached the memory access stage, the interrupt service routine as address of the previous interrupt stored in the register is used as the return address, and is stored in the working space, so that the next interrupt can be processed immediately.

Method and apparatus for fast response time interrupt control in a pipelined data processor

A data processing system for decoding instructions in parallel in a superscalar, complex instruction set computing (CISC) computer. In a training mode of operation, an encrypter 29 encrypts preprocessed instructions retrieved from an instruction cache 26. In a processing mode of operation, instruction information is fetched and decrypted in decrypter 30. A prefetcher 21 separates the fetched instruction according to the decrypted boundary information. An instruction length verifier 25 verifies that the instructions were separated correctly and controls decoders 22a-c according to the verification. If the verification is correct for a given set of instructions, the system processes the instructions in parallel through the decoders to a dispatch logic circuit 23 and then to functional units 24. If the verification is incorrect, those related instructions may be needed to decode serially.

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Kaohsiung, Taiwan

Shisheng Shang