Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Shiro Yoshioka

Seiji Yamaguchi

Kenichi Kawaguchi

Toshiya Kai

Toru Kakiage

Koutarou Hirai

Tomohiro Kurozumi

Masahiko Matsumoto

Hidenori Nanki

Shigenori Satoh

Shinichiro Fukai

An information processing apparatus comprising a secure information unit that is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and that is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Information processing apparatus for accessing memory spaces including a user memory space and a secure memory space

An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has entered the power supply terminal thereof. When the incoming noise reaches relatively low Level 1(L), important information, determining the state of the CPU, is protected by saving it on a register. Thereafter, when the noise level exceeds Level 1(H), important information, representing the status of the predetermined process, is protected by storing it on a memory. Subsequently, when the noise level reaches Level 2, the CPU is suspended. And when the noise has decreased to less than Level 1(L), the predetermined process is resumed in accordance with the information saved and protected on the register and memory. Accordingly, even if noise has entered, the predetermined process can be continued without causing runway in the CPU after having been suspended for a while.

Apparatus and method for processing information continuously even against extraneously incoming noise

A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.

Control systems having an address conversion device for controlling a

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Hyogo, Japan

Shiro Yoshioka