Panasonic Corporation

Socionext Inc.

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Shiro Usami

Daisuke Matsuoka

Katsuya Arai

Masahiro Gion

Toshihiro Kohgami

Masato Maede

Naoki Nojiri

Hiroaki Yabu

Shinji Kinuyama

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Semiconductor integrated circuit device

Semiconductor integrated circuit device having an ESD protection circuit

A semiconductor integrated circuit includes a power supply switch circuit which uses a PMOS transistor and an NMOS transistor to select a first power supply voltage applied to a first power supply input terminal or a second power supply voltage applied to a second power supply input terminal, and output the selected voltage as a power supply voltage to a third power supply output terminal, a first switch control circuit connected to the gate of the PMOS transistor, and a second switch control circuit connected to the gate of the NMOS transistor.

Semiconductor integrated circuit

A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows&#xd7;n columns from a corner of the chip above the corner portion.

Semiconductor integrated circuit chip and layout method for the same

A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL&#x3e;tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact. Thus, convergence of the current at the contact holes of the diffusion layer of the anode is reduced, so that the reliability of the diode element improves.

Semiconductor integrated circuit and system LSI including the same

In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes Wand Wexceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes Wand Wvia parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N, Nand two N-type low-voltage transistors N, Nfor receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Level shift circuit

In a level shift circuit, even when a power supply voltage of an input signal is reduced, a level shift operation is reliably performed without causing increase in circuit area and process costs. For a pair of n-type transistors which receive an input signal and a reverse signal of the input signal as a pair of complementary signals at their gates, respectively, a layout which allows reduction in unit gate width size is adopted. The layout configuration includes a plurality of divided rectangular doped regions which function as drains and sources and a plurality of gates arranged to align in a gate length direction with a gate width direction according with a short side direction of the doped regions. The gates are electrically connected with one another, the drains are electrically connected with one another, and the sources are electrically connected with one another.

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Osaka, Japan

Shiro Usami