Fujitsu Corporation

Fujitus Limited

Shiro Uriu

Satoshi Kakuma

Shuji Yoshimura

Masami Murayama

Kenichi Okabe

Noriko Samejima

Yoshihiro Uchida

Hiroshi Furukawa

Yasuhiro Aso

Tetsuo Kawano

Naoyuki Izawa

Jin Abe

Kazuo Hajikano

Ichiro Kasama

Mitsuharu Wakayoshi

Kazuaki Imafuku

Hiroya Kawasaki

Kazumasa Sonoda

Yoshihiro Watanabe

Yoshiharu Kato

Hiroshi Tomonaga

Naoki Matsuoka

Takashi Hatano

Miyoshi Saito

Mikio Nakayama

Jun Itoh

Hisanori Fujisawa

Eiji Ishioka

Hiroshi Nishida

Shigeru Sekine

Satoshi Esaka

Miyuki Kawataka

Naoki Fukuda

Masaki Kira

Yoshiyuki Karakawa

Fumio Hirase

Yasuhiro Nishikawa

Shinichi Araya

Nobuyuki Tsutsui

Tetsuaki Wakabayashi

Atsushi Kagawa

Atsuko Suzuki

Shouji Kohira

Hiromi Yamanaka

Yoshihisa Tsuruta

Yukinaga Toyoda

Tetsu Tanizawa

Toshiaki Suzuki

Hideki Yoshizawa

Kenichi Kawarai

Yuzo Okuyama

Koki Mie

Norio Suzuki

Tadashi Hoshino

Ryo Takajitsuko

Masakatsu Nagata

Yoshio Morita

Yasusi Kobayasi

Hiroshi Ishiwata

Yasusi Kobayashi

Masanobu Furukoshi

Noaki Fukuda

An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Data buffer control which controls selection of path and operation of data buffer, based on stored configuration information

A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Array processor having reconfigurable data transfer capabilities

A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.

Intra-station control system for connectionless communications system

A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.

Communications apparatus and congestion control method

Packets input from input HWs #to #to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4&#xd7;4 switches. The 4&#xd7;4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4&#xd7;4 switches after being switched are alternately multiplexed, and output to output HWs #through #. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

Packet switch device

A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Processor and pipeline reconfiguration control method

A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.

Switching apparatus, communication apparatus, and communication system

In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Address release method, and common buffering device for ATM switching system which employs the same method

A service identification adding portion adds service identification information to a cell corresponding to each connection that uses a predetermined communication service (ABR service) and that is input to a switch system. A connection number counting portion counts the number of connections that use the communication service on each output line at predetermined intervals. A band control information generating portion generates band control information corresponding to each output line at predetermined intervals based on the number of connections counted at predetermined intervals. A band control information indicating portion sends band control information at predetermined intervals corresponding to each output line to a transmission side terminal corresponding to a connection that uses the communication service on each output line.

Band controlling apparatus

A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.

Communication controlling apparatus

A peripheral device cable, connected to a peripheral device, integrally incorporates a subscriber link that is a physical line for transmitting subscriber information in synchronization with a highway clock and a control link that is a physical line for transmitting control data in synchronization with the highway clock. A control data converter controls interfacing between the control data transferred over the control link synchronously with the highway clock and control data that a control unit transmits/receives asynchronously with the highway clock. The subscriber link is connected to a switch.

In-station control system and method

The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S,). The output message identifier MID is reserved (S,), and the tag information and output MID are assigned to the BOM (S,). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S,and S,). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S,and S,). Then, the output MID is released (S,).

Connectionless communications system, its test method, and intra-station control system

Four SR modules are provided in the second stage of a 3-stage MSSR switch. To guarantee the MSSR switch the capacity of 20 Gbps, SR modules are provided in each of the first and third stages of the switch. When the capacity of the MSSR switch is extended from 20 Gbps to 40 Gbps, SR modules are added to both of the first and third stages and connected to the four SR modules in the second stage. To further extend the capacity of the MSSR switch to 60 or 80 Gbps, the SR modules are sequentially added to the first and third stages, and the newly provided SR modules are connected to the four SR modules in the second stage.

Multistage connection switch and extension method

A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device. The simplex unit executes predetermined control upon accepting control data from the apparent acting device.

Apparatus for preventing malfunction at time of duplex unit failure

A cell count identifier inserting portion for inserting a cell count identifier into the header portion of a cell is provided at a predetermined position within an exchange and a plurality of cell counting portions for counting a cell into which a cell count identifier is inserted are provided on the downstream side of the cell count identifier inserting portion. A cell loss detecting portion compares the number of cells into which the cell count identifier is inserted with the number of cells counted by each of the cell counting portions, detects cell loss on the basis of the result of the comparisons and specifies the section in which cell loss is caused, if the cell loss is detected.

Method of detecting cell loss and exchange provided with cell loss

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Kawasaki, Japan

Shiro Uriu