Intel Corporation

Shiro Suzuki

Bill Check

Vicky P Duerk

Jesus Palomino Echartea

Samuel S Rhodes

Guillermo Lopez Lopez

A memory stores data for transfer over a bus by a computer program that operates according to a bus frame protocol. The memory includes a data structure stored in the memory. The data structure includes a matrix having blocks arranged in N rows and M columns, where N and M are integers that are greater than one. A block of the matrix includes data used with the bus frame protocol and corresponds to a destination port and a time slot for the data.

Bus frame protocol

A transceiver for switching signals between a transmission line and a networked system includes a cross connect for switching payload information and a processor for switching signaling information. The payload and signaling information is formatted into time slots in frames transmitted and received over the transmission line, e.g., a T line. The payload and signaling information is switched according to a time slot interchange map. The processor may switch the signaling information between the line side and system side of the transceiver by a stable signaling value for a time slot ad writing that value to an appropriate memory location in a line side register on a system side register, depending on the direction of data flow.

Integrated signaling / payload cross connect architecture

A cross connect with a cascadable architecture may selectively output a switched or an unswitched data stream from a transmission line. Two or more such cross connects may be cascaded by connecting their system side ports for bi-directional communication. Either of the cross connect connected directly to the transmission line or the cross connect connected indirectly to the transmission line through the other cross connect may switch the data stream from the transmission line for output to a system.

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Folsom, CA, United States of America

Shiro Suzuki